Patents by Inventor Nicolas J. Loubet

Nicolas J. Loubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189766
    Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Nicolas J. Loubet, Sanjay C. Mehta, Vijay Narayanan, Muthumanickam Sankarapandian
  • Patent number: 10319676
    Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
  • Patent number: 10304936
    Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas J. Loubet, Sanjay C. Mehta, Vijay Narayanan, Muthumanickam Sankarapandian
  • Patent number: 10297665
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Nicolas J. Loubet, Devendra K. Sadana
  • Patent number: 10262900
    Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Publication number: 20190109177
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Inventors: Daniel Chanemougame, Julien Frougier, Nicolas J. Loubet, Ruilong Xie
  • Patent number: 10249739
    Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega
  • Publication number: 20190096669
    Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Nicolas J. Loubet, Binglin Miao, Muthumanickam Sankarapandian, Charan V. Surisetty, Chun W. Yeung, Jingyun Zhang
  • Patent number: 10242920
    Abstract: Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet, Muthumanickam Sankarapandian
  • Patent number: 10177226
    Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet
  • Publication number: 20190006462
    Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.
    Type: Application
    Filed: August 14, 2018
    Publication date: January 3, 2019
    Inventors: Michael A. Guillorn, Nicolas J. Loubet
  • Patent number: 10170552
    Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner. The liner protects the second channel material from the wet etch.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Isaac Lauer, Nicolas J. Loubet
  • Publication number: 20180374761
    Abstract: Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.
    Type: Application
    Filed: June 29, 2018
    Publication date: December 27, 2018
    Inventors: Michael A. Guillorn, Nicolas J. Loubet, Muthumanickam Sankarapandian
  • Publication number: 20180323278
    Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 8, 2018
    Inventors: Bruce B. Doris, Hong He, Nicolas J. Loubet, Junli Wang
  • Publication number: 20180301557
    Abstract: A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 18, 2018
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Publication number: 20180277626
    Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 27, 2018
    Inventors: Michael A. Guillorn, Isaac Lauer, Nicolas J. Loubet
  • Patent number: 10074575
    Abstract: Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first sacrificial nanosheet and forming a first nanosheet stack over the first sacrificial nanosheet, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial nano sheets. The method further includes exposing a surface area of the first sacrificial nanosheet and exposing surface areas of the alternating channel nanosheets and sacrificial nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and sacrificial nanosheets. The method further includes applying an etchant to the exposed surface areas, wherein the etchant is selective based at least in part on the amount of surface area to which the etchant is applied.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet, Muthumanickam Sankarapandian
  • Publication number: 20180254329
    Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Inventors: Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega
  • Publication number: 20180226296
    Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
    Type: Application
    Filed: March 30, 2018
    Publication date: August 9, 2018
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 10043748
    Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet