Patents by Inventor Nicolas Jean
Nicolas Jean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131136Abstract: The present invention is in the field of pneumococcal capsular saccharide conjugate vaccines. Specifically, the present invention relates to sized Streptococcus pneumoniae serotype 6A capsular polysaccharides, in particular Streptococcus pneumoniae serotype 6A capsular polysaccharides having the average size (e.g. Mw) of the Streptococcus pneumoniae serotype 6A capsular polysaccharide is between 100-1000 kDa, suitably conjugated to a carrier protein.Type: ApplicationFiled: November 1, 2023Publication date: April 25, 2024Applicant: GLAXOSMITHKLINE BIOLOGICALS SAInventors: Elisabeth Marie Monique BERTAUD, Ralph Leon BIEMANS, Nicolas Jean Benoit MONIOTTE, Laurent Bernard Jean STRODIOT
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Publication number: 20240128346Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.Type: ApplicationFiled: October 12, 2022Publication date: April 18, 2024Inventors: Julien Frougier, Andrew M. Greene, Shogo Mochizuki, Ruilong Xie, Liqiao Qin, Gen Tsutsui, Nicolas Jean Loubet, Min Gyu Sung, Chanro Park, Kangguo Cheng, Heng Wu
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Publication number: 20240117080Abstract: A catalytic system based on at least one rare-earth metallocene and an organomagnesium reagent as co-catalyst of formula RB—(Mg—RA)m—Mg—RB is provided. According to the formula, RB comprises a benzene nucleus substituted with the magnesium atom. One of the carbon atoms of the benzene nucleus ortho to the magnesium is substituted with a methyl, an ethyl or an isopropyl or forms a ring with the carbon atom which is its closest neighbour and which is meta to the magnesium. The other carbon atom of the benzene nucleus ortho to the magnesium is substituted with a methyl, an ethyl or an isopropyl. RA is a divalent aliphatic hydrocarbon-based chain, optionally interrupted with one or more oxygen or sulfur atoms or with one or more arylene groups. The m is a number greater than or equal to 1, preferably 1. The catalytic system allows the synthesis of dienic and/or ethylenic telechelic polymers.Type: ApplicationFiled: November 19, 2021Publication date: April 11, 2024Inventors: Robert NGO, Nicolas BAULU, Christophe BOISSON, Franck D'AGOSTO, François JEAN-BAPTISTE-DIT-DOMINIQUE, Julien THUILLIEZ
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Publication number: 20240113023Abstract: A semiconductor device includes a backside power line located under a p-channel field effect transistor region and an n-channel field effect transistor region; a backside signal line located between the p-channel field effect transistor region and the n-channel field effect transistor region; and an airgap between the backside power line and the backside signal line.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Tao Li, Ruilong Xie, Nicolas Jean Loubet, Julien Frougier
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Publication number: 20240096947Abstract: Embodiments of the present invention are directed to the implantation of composite tunnel field effect transistors (TFETs) in a nanosheet process. In a non-limiting embodiment of the invention, a first source or drain region is formed having a first composition and a first doping type. A second source or drain region is formed having a second composition and a second doping type opposite the first doping type. A first composite channel structure is formed between the first source or drain region and the second source or drain region. The first composite channel structure includes a first nanosheet trimmed to expose extension portions of the first source or drain region and extension portions of the second source or drain region. The first composite channel structure further includes a first channel epitaxy wrapping around the trimmed first nanosheet. The first channel epitaxy is connected laterally to the extension portions.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventors: Kirsten Emilie Moselund, Nicolas Jean Loubet, Bogdan Cezar Zota, Shogo Mochizuki
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Publication number: 20240096952Abstract: A semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Juntao Li, Ruilong Xie, Julien Frougier, Nicolas Jean Loubet
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Publication number: 20240096940Abstract: A microelectronic structure including a first transistor including a plurality a first channel layers. A second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. A dielectric bar located between the first transistor and the second transistor. A first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. A first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. A second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Tao Li, Ruilong Xie, Julien Frougier, Nicolas Jean Loubet
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Patent number: 11935120Abstract: A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.Type: GrantFiled: June 8, 2021Date of Patent: March 19, 2024Assignee: Liquid-Markets GmbHInventors: Seth Gregory Friedman, Alexis Nicolas Jean Gryta, Thierry Gibralta
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Publication number: 20240082376Abstract: The present application relates to arenaviruses with rearrangements of their open reading frames (“ORF”) in their genomes. In particular, described herein is a modified arenavirus genomic segment, wherein the arenavirus genomic segment is engineered to carry a viral ORF in a position other than the wild-type position of the ORF. Also described herein are trisegmented arenavirus particles comprising one L segment and two S segments or two L segments and one S segment. The arenavirus, described herein may be suitable for vaccines and/or treatment of diseases and/or for the use in immunotherapies.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Daniel David Pinschewer, Doron Merkler, Sandra Margarete Kallert, Mario Kreutzfeldt, Stéphanie Gabrielle Darbe Abdelrahman, Nicolas Jean Page
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Patent number: 11928796Abstract: Encoding can involve correcting chroma components representing the chroma of an input image according to a first component representing a mapping of the luminance component of said input image used for reducing or increasing the dynamic range of said luminance component, and a reconstructed component representing an inverse mapping of said first component. At least one correction factor according to said at least one scaled chroma components can also be obtained and transmitted. Decoding can involve scaled chroma components being obtained by multiplying chroma components of an image by at least one corrected chroma correction function depending on said at least one correction factor. Components of a reconstructed image can then be derived as a function of said scaled chroma components and a corrected matrix that depends on an inverse of a theoretical color space matrix conversion and said at least one correction factor.Type: GrantFiled: November 30, 2018Date of Patent: March 12, 2024Assignee: InterDigital Patent Holdings, Inc.Inventors: Marie-Jean Colaitis, David Touze, Nicolas Caramelli
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Publication number: 20240079327Abstract: A semiconductor device includes a transistor disposed on a semiconductor substrate, wherein the transistor includes a source/drain region disposed on a first side of the semiconductor substrate. A via extends through the semiconductor substrate, and connects a power element disposed on a second side of the semiconductor substrate to the source/drain region. A dielectric spacer is disposed between the via and the semiconductor substrate.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Ruilong Xie, Theodorus E. Standaert, Nicolas Jean Loubet, Kisik Choi
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Patent number: 11922918Abstract: A noise controlling method includes generating a reference signal representing a primary noise, generating a secondary noise in response to a control signal for cancelling the primary noise, generating an error signal representing a superposition of the primary and secondary noises at a position, generating an additional reference signal, secondary noise, or additional error signal, and generating the control signal for generating the secondary noise using adaptive subband filtering based on the reference and error signals, the generating the control signal including decomposing the reference signal and the error signal into a subband reference and error signal for each subband, updating subband adaptive filters for a subband based on the subband reference signal and the subband error signal, updating a fullband adaptive filter based on the updated subband adaptive filter, and generating the control signal by filtering the reference signal by the updated fullband adaptive filter.Type: GrantFiled: July 9, 2020Date of Patent: March 5, 2024Assignee: Faurecia Creo ABInventors: Nicolas Jean Pignier Delafontaine, Christophe Mattei, Robert Risberg
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Publication number: 20240074135Abstract: A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Nicolas Jean Loubet, Kirsten Emilie Moselund, Bogdan Cezar Zota
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Publication number: 20240063189Abstract: A long channel transistor structure including a first transistor array adjacent to a second transistor array, a third transistor array adjacent to a fourth transistor array, where the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array, and a continuous channel path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Heng Wu, Ruilong Xie, Julien Frougier, Min Gyu Sung, Nicolas Jean Loubet
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Patent number: 11879341Abstract: A turbine for a turbine engine extending along an axis includes an annular casing and at least one turbine stage having a nozzle and a rotor impeller wheel surrounded by a sealing ring with an abradable element. The impeller wheel and the sealing ring are located downstream of the nozzle, and the sealing ring has an upstream end held on the casing by locking means. The turbine includes elastic sealing means in contact with the locking means as well as with the nozzle or the casing so as to press the locking means against the sealing ring. The locking means includes a radially outer portion with a C-shaped cross-section and a radial portion extending radially inwards from the outer portion. The sealing means include two elastic seals bearing on the radial portion, respectively, on either side of the radial portion.Type: GrantFiled: April 12, 2021Date of Patent: January 23, 2024Assignee: SAFRAN AIRCRAFT ENGINESInventors: Simon Nicolas Morliere, Nicolas Jean-Marc Marcel Beauquin, Stéphane Sylvain Bois, Sébastien Philippe Edith Bourgeois
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Patent number: 11865922Abstract: A drive arrangement for a vehicle, the drive arrangement comprising a rotatable interface arranged to be mounted to the vehicle, wherein the rotatable interface is rotatably coupled to a mounting arm to allow continuous rotation of the mounting arm in a clockwise and anti clockwise direction that is substantially perpendicular to the longitudinal and transverse axis of the vehicle; and a first electric motor having a stator and a rotor, wherein the stator is coupled to the mounting arm to allow the axis of the rotor to be substantially perpendicular to the rotational axis of the rotatable interface, wherein the rotor is arranged to be coupled to a wheel of the vehicle to allow the electric motor to provide drive torque to the wheel.Type: GrantFiled: March 30, 2020Date of Patent: January 9, 2024Assignee: Protean Electric LimitedInventors: Jonathan Bernard Ameye, Cyril Aime Gerland, Nicolas Jean Albert Allain
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Publication number: 20240006467Abstract: A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Julien Frougier, Sagarika Mukesh, Anthony I. Chou, Andrew M. Greene, Ruilong Xie, Nicolas Jean Loubet, Veeraraghavan S. Basker, Junli Wang, Effendi Leobandung, Jingyun Zhang
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Patent number: 11862139Abstract: A method and a system for creating a plurality of sound zones within an acoustic cavity is provided. The method comprises: providing a plurality of actuators within the acoustic cavity, each for generating a respective acoustic output in response to a respective drive signal, providing, for each of the plurality of actuators, an adaptive filter for receiving a respective input signal, and generating a respective output signal, providing, for each of the adaptive filters, at least one filter coefficient, providing a plurality of error sensors within the acoustic cavity, each for generating a respective error signal e, representing a respective sound detected by the respective error sensor, providing an audio data signal x(n) for generating a desired sound in a desired sound zone of the plurality of sound zones, determining, for the desired sound zone, a set of actuator generation coefficients kgk, a set of actuator exclusion coefficients kek, wherein k refers to a kth actuator, k=1, 2, 3 . . .Type: GrantFiled: January 14, 2020Date of Patent: January 2, 2024Assignee: Faurecia Creo ABInventor: Nicolas Jean Pignier
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Patent number: 11858201Abstract: A method for manufacturing a part made from composite material of a thermoplastic or thermosetting matrix reinforced with fibers includes producing a structure of fibers, that is optionally pre-impregnated. The method further includes aligning and juxtaposing fibers, while stretching them between return elements, and keeping them separated from each other, so as to obtain a first layer. The method includes superimposing, on said first layer, a second layer obtained in an identical manner to the first, in which the fibers are parallel to those of the first layer and kept apart from it. The method includes repeating the superimposing operation until the desired thickness is obtained and stiffening the material making up the matrix (M) by a method that suits its nature.Type: GrantFiled: June 4, 2019Date of Patent: January 2, 2024Assignee: CONSEIL ET TECHNIQUEInventors: Guy Valembois, Nicolas-Jean Fischer, Bertrand Florentz
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Publication number: 20230411289Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.Type: ApplicationFiled: May 24, 2022Publication date: December 21, 2023Inventors: Ruilong Xie, Kisik Choi, Junli Wang, Somnath Ghosh, Julien Frougier, Min Gyu Sung, Theodorus E. Standaert, Nicolas Jean Loubet, Huiming Bu