Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.

Abstract: A first source drain region adjacent to a first transistor, a second source drain region adjacent to a second transistor, an upper source drain contact above the first source drain region, a bottom source drain contact below the second source drain region, the bottom and the upper source drain contacts are on opposite sides, a horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of dielectric side spacers surrounding the second source drain region. An embodiment where a bottom source drain contact surrounds vertical sides of a source drain region. A method including forming a forming a first and a second nanosheet stacks, forming a top source drain contact to a first source drain region adjacent to the first nanosheet stack, forming a bottom source drain contact to a lower horizontal surface of a second source drain region adjacent to the second nanosheet stack.

Abstract: A semiconductor device includes a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation. The semiconductor device further includes an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation. The semiconductor device further includes a gate surrounding the first channels and the second channels.

Abstract: A semiconductor structure including a gate-all-around input/output (I/O) device and a gate-all-around core logic device integrated on a semiconductor substrate is provided. The gate-all-around I/O device, which has a wider channel length than the gate-all-around core logic device, has a dielectric spacer and/or inner spacers that is (are) laterally wider (i.e., thicker) than a dielectric spacer and/or inner spacers present in the gate-all-around core logic device.

Abstract: A gate-all-around transistor structure including a channel region surrounded on three sides by a gate conductor, and a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor.

Abstract: The present invention is in the field of pneumococcal capsular saccharide conjugate vaccines. Specifically, the present invention relates to sized Streptococcus pneumoniae serotype 6A capsular polysaccharides, in particular Streptococcus pneumoniae serotype 6A capsular polysaccharides having the average size (e.g. Mw) of the Streptococcus pneumoniae serotype 6A capsular polysaccharide is between 100-1000 kDa, suitably conjugated to a carrier protein.

Abstract: Embodiments of present invention provide a method of forming a nanosheet transistor structure. The method includes forming a nanosheet stack on a substrate, the nanosheet stack having a set of nanosheets separated by a set of sacrificial sheets; forming a vertical dielectric pillar separated from the nanosheet stack; forming a dielectric liner lining the nanosheet stack and the vertical dielectric pillar; forming a set of inner spacers between the set of nanosheets; forming a side spacer between the set of inner spacers and the vertical dielectric pillar, the side spacer being surrounded by the dielectric liner at least at a left side between the set of inner spacers and the side spacer and at a right side between the side spacer and the vertical dielectric pillar; and forming a replacement gate stack surrounding the set of nanosheets. A structure formed thereby is also provided.

Abstract: A method and apparatus for enabling compression of a stream of pictures according to a target bit rate are described. A first configuration parameter for a first portion is determined based at least in part on a first relative weight of the first portion with respect to a first set of N portions, where the first set of N portions includes the first portion and N-1 portions which succeed the first portion. A second configuration parameter for a second portion of a second picture is determined based at least in part on a second relative weight of the second portion with respect to a second set of M portions of pictures, where the second set of M portions includes a subset of the N-1 portions from the first set and zero or more additional portions of pictures from the stream of pictures.

Abstract: A ceramic and a method of forming a ceramic including milling steel slag exhibiting a diameter of 5 mm of less to form powder, sieving the powder to retain the powder having a particle size in the range of 20 to 400 removing free iron from the powder with a magnet, heat treating the powder at a temperature in the range of 700° C. to 1200° C. for a time period in the range of 1 hour to 10 hours and oxidizing retained iron in the powder, compacting the powder at a compression pressure in the range of 20 MPa to 300 MPA, and sintering the powder at a temperature in the range of 700° C. to 1400° C. for a time period in the range of 0.5 hours to 4 hours to provide a ceramic.

Abstract: To simplify architecture of a measurement device for affixing to a wall of a moving object or stationary object located in a flow, a device includes a support having compartments with an opening that opens to the exterior of the support at the free face in which sensors are housed, the support having a free face and a face to come into contact with the wall, the free face being opposite the face. The device includes a cavity with a printed circuit board, the compartments including an opening that opens to the exterior of the support in the cavity. The cavity is made in the free face opening into it. The circuit board is upside down in the cavity with the printed face towards the interior of the support. The sensors attached to the circuit board are suspended in the compartments. The unprinted face affords an aerodynamic smooth and planar surface.

Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Abstract: A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.

Abstract: A semiconductor structure including a first stacked transistor structure including a top device stacked directly above a bottom device, and a second stacked transistor structure adjacent to the first stacked transistor, the second stacked transistor including a top device stacked directly above a bottom device, where the top device of the first stacked transistor structure and the top device of the second stacked transistor structure are made from different gate dielectric materials, and where the bottom device of the first stacked transistor structure and the bottom device of the second stacked transistor structure are made from different gate dielectric materials.

Abstract: The present invention relates to a device for cooling, using air jets, an external casing of a turbomachine, comprising a housing for supplying air to cooling tubes of said casing, the housing being provided with an attachment device on the external casing. According to the invention, said attachment device comprises two upstream ball joint retention devices which each connect the housing to the external casing.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

Abstract: The present invention relates to a kit comprising a microphone and a headphone, and also a case member provided with a first cut-out region for accommodating the microphone and a second cut-out region for accommodating the headphone as well as electronics means for charging the microphone and/or the headphone; the microphone comprising: a sound-receiving portion; a headphone connecting portion; an extension portion connecting a distal end arranged to connect to the sound-receiving portion and a proximal end opposite the distal end thereof and arranged to connect to the headphone connecting portion, the proximal end extending a distance from the distal end such that a voice signal received is greater than the environmental noise thus yielding a higher signal to noise ratio; the headphone comprising: a main body portion dimensioned for adapting to the user's ear contour to retain the headphone on the ear; a microphone connecting portion provided on the main body portion; each of the headphone connecting portion

Abstract: The subject matter herein includes apparatus and techniques, such as can be used to automatically assess dominance of sensation. For example, a technique for such assessment can include generating a representation of two or more sensations for display to a user, receiving respective selections of respective sensations amongst the two or more sensations in response to display of the representation. As an example, receiving the respective selections of respective sensations can include obtaining data indicative of a magnitude of the respective sensations corresponding to the respective selections and obtaining data indicative of a temporal relationship between the respective selections, providing time-intensity and dominance of sensation data contemporaneously.

Abstract: The invention proposes an aeronautical turbine engine assembly comprising an upstream casing (55) to which guide blading (48a) is fastened, and a downstream casing (58) to which a sealing element (62) provided with an abradable material for rotor blading is fastened. This assembly further comprises a shroud ring (66) placed between the upstream casing and the downstream casing and fastening means (68) for detachably fastening the shroud ring. In order to be fastened to the upstream casing, the guide blading (48a) of the turbine engine is mounted on a downstream hook (480b) of the upstream casing, without being hooked onto the shroud ring (66), and the downstream casing (58) has an upstream hook with which the sealing element (62) is engaged in order to be fastened to the downstream casing, or the shroud ring has an upstream hook on which the sealing element (62) is mounted so as to be fastened to the downstream casing.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: An electronic device interfaced with a multiple digital signatures security engine, internally or externally, which enable the device to obtain PUF-based security credentials with the option to generate multiple unique digital signatures from the same source of PUF entropy. The multiple digital signatures security zone includes a source of PUF entropy dynamically measurable, a non-volatile memory storage media and a digital circuitry performing all the functions requested by the electronic device interfaced. The electronic device is able to select and switch between which unique digital signature to be involved for its related cybersecurity applications without depending on power-up sequences or single time operations after power-up sequence.