Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.

Abstract: An barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier slack includes first and second barrier layers formed from, for example, Ir, Ru, Pd, Rh, or alloys thereof. The first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation (RTO) prior to formation of the second barrier layer. The RTO forms a thin oxide layer on the surface of the first barrier layer. The thin oxide layer passivates the grain boundaries of the first barrier layer as well as promoting mismatching of the grain boundaries of the first and second barrier layer.

Abstract: A fabrication process for ferroelectric capacitors includes forming openings 23, 30, in the device, into which electrically conductive material 28, 37 can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer 24, 34 of getter material which absorbs contaminants 25, 31, 33 formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers 7 of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.

Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.

Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.

Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

Abstract: An layer for a structure such as a ferro-capacitor is formed by a three stage process consisting of (i) applying a wetting layer 23 over some or all of the structure 21, (ii) applying a second layer 25 of a second material over the wetting layer 23, and (iii) transforming the second material by a chemical reaction. In an example, the second material is Al, and step (iii) inclues oxidising the Al layer 25 to form an Al2O3 layer 27. The wetting layer 21 is preferably applied by a process having good step coverage even in high aspect regions of the substrate, even though that process may have a low deposition rate. The wetting layer 21 is preferably formed of a material over which the second material has a high mobility, so that the aluminium layer—and the subsequent Al2O3 layer—are relatively uniform in thickness. Step (iii) may be preceded by a step of enhancing lateral mobility of the second material, e.g. by a heat treatment.

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

Abstract: A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.

Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.

Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers having mismatched grain boundaries. The barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second barrier layer.

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

Abstract: An improved barrier stack for reducing plug oxidation in capacitor-over-plug structures is disclosed. The barrier stack is formed on a non-conductive adhesion layer of titanium oxide. The barrier stack includes first and second barrier layers wherein the second barrier layer covers the top surface and sidewalls of the first barrier layer. In one embodiment, the first barrier layer comprises Ir and the second barrier layer comprises IrOx. Above the barrier stack is formed a capacitor.

Abstract: The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen content. The oxygen-containing iridium layer is stale at temperatures up to 800° C. and withstands the formation of iridium silicide upon contact with the silicon-containing layer. Such micro-electronic structures are preferably used in semiconductor memories.

Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.

Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.