Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract: The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen content. The oxygen-containing iridium layer is stale at temperatures up to 800° C. and withstands the formation of iridium silicide upon contact with the silicon-containing layer. Such micro-electronic structures are preferably used in semiconductor memories.

Abstract: A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant including hydrofluoric acid. The diffusion barrier layer is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.

Abstract: A microelectronic structure has an adhesion layer which is disposed between a base substrate and a barrier layer. The adhesion layer improves the adhesion of the barrier layer on the base substrate, in particular to insulation layers provided there. Microelectronic structures of this type are preferably used in semiconductor memories. A method of fabricating such a microelectronic structure is also provided.

Abstract: An electronic material is expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.I is at least one sort of noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M.sub.II is at least one sort of transition metal selected from the group consisting of Hf, Ta, Zr, Nb, V, Mo and W) having a composition within the range of 90.gtoreq.a.gtoreq.40, 15.gtoreq.b.gtoreq.2, 4.ltoreq.c and a+b+c=100. A dielectric capacitor comprises: a diffusion preventing layer made of the material expressed by the composition formula M.sub.ia M.sub.IIb O.sub.c ; a lower electrode on the diffusion preventing layer; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. Another dielectric capacitor comprises: a diffusion preventing layer made of a material expressed by the composition formula M.sub.Ia M.sub.IIb O.sub.c (where a, b and c are compositions in atomic %, M.sub.

Abstract: A capacitor structure of a semiconductor memory cell such as a FERAM has an upper electrode less susceptible a damage even by heat-treatment in a hydrogen gas atmosphere. The capacitor structure includes a lower electrode, a capacitor thin film formed of a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the capacitor thin film. The upper electrode is made of Ru.sub.1-x O.sub.x (0.1<x<0.64).

Abstract: A capacitor structure of a semiconductor memory cell such as a FERAM has an upper electrode less susceptible a damage even by heat-treatment in a hydrogen gas atmosphere. The capacitor structure includes a lower electrode, a capacitor thin film formed of a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the capacitor thin film. The upper electrode is made of Ru.sub.1-x O.sub.x (0.1<x<0.64).