Patents by Inventor Nicolas POSSEME

Nicolas POSSEME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210090880
    Abstract: A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 25, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Frédéric LE ROUX
  • Publication number: 20210066133
    Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.
    Type: Application
    Filed: August 10, 2020
    Publication date: March 4, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Cyrille LE ROYER, Fabrice NEMOUCHI
  • Publication number: 20210057283
    Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 25, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas POSSEME
  • Patent number: 10928725
    Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier, Christophe Navarro
  • Patent number: 10923352
    Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 16, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier
  • Publication number: 20210013089
    Abstract: A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Publication number: 20210013040
    Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE GRENOBLE ALPES
    Inventors: Nicolas POSSEME, Marceline BONVALOT, Ahmad CHAKER, Christophe VALLEE
  • Publication number: 20210005443
    Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained
    Type: Application
    Filed: June 29, 2020
    Publication date: January 7, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Loic GABEN, Cyrille LE ROYER, Fabrice NEMOUCHI, Nicolas POSSEME, Shay REBOH
  • Patent number: 10875236
    Abstract: A method for etching a layer of assembled block copolymer including first and second polymer phases, the etching method including a first step of etching by a first plasma formed from carbon monoxide or a first gas mixture including a fluorocarbon gas and a depolymerising gas, the first etching step being carried out so as to partially etch the first polymer phase and to deposit a carbon layer on the second polymer phase, and a second step of etching by a second plasma formed from a second gas mixture including a depolymerising gas and a gas selected among the carbon oxides and the fluorocarbon gases, the second etching step being carried out so as to etch the first polymer phase and the carbon layer on the second polymer phase.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 29, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Sébastien Barnola, Patricia Pimenta Barros, Aurélien Sarrazin
  • Publication number: 20200335327
    Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.
    Type: Application
    Filed: May 23, 2017
    Publication date: October 22, 2020
    Inventors: Raluca TIRON, Nicolas POSSEME, Xavier CHEVALIER
  • Publication number: 20200335343
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia NOURI, Stefan LANDIS, Nicolas POSSEME
  • Patent number: 10795257
    Abstract: A method for forming a functionalised guide pattern for the self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern made of a first material having a first chemical affinity for the block copolymer, the guide pattern having a cavity with a bottom and side walls; grafting a functionalisation layer made of a second polymeric material having a second chemical affinity for the block copolymer, the functionalisation layer having a first portion grafted onto the bottom of the cavity and a second portion grafted onto the side walls of the cavity; selectively etching the second portion of the functionalisation layer relative to the first portion of the functionalisation layer, the etching including a step of exposure to an ion beam following a direction that intersects the second portion of the functionalisation layer, such that the ion beam does not reach the first portion of the functionalisation layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 6, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier
  • Patent number: 10784108
    Abstract: A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 22, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Guillaume Claveau, Maxime Argoud, Nicolas Posseme, Raluca Tiron
  • Patent number: 10741398
    Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia Nouri, Stefan Landis, Nicolas Posseme
  • Publication number: 20200251570
    Abstract: There is provided a method for etching a dielectric layer covering at least partially a flank of a structure made of a semi-conductive material, the structure having at least one face, the method including a plurality of sequences, each including at least the following steps: a main oxidation so as to form an oxide film; a main anisotropic etching of the oxide film, carried out so as to etch a portion of the oxide film extending parallel to the flanks and at least some of the dielectric layer, be stopped before etching the structure and a whole thickness of another portion of the oxide film extending perpendicularly to the flanks, the steps being repeated until the complete removal of the dielectric layer located on the flanks of the structure.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 6, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas POSSEME, Vincent Ah-Leung, Olivier Pollet
  • Publication number: 20200251569
    Abstract: There is provided a method for producing a transistor with a raised source and drain the method including depositing a layer on the gate pattern and the active layer; carrying out an isotropic modification of the layer over a thickness to obtain a first portion of modified layer, carrying out an anisotropic modification of the layer over another thickness, along a direction normal to the active layer, to obtain second portions of modified layer, by conserving portions of non-modified layer on the flanks of the gate pattern and at the foot of the gate pattern, removing the first and second modified portions by conserving the portions, by selective etching, to form spacers having an L-shape, epitaxially growing the source and drain in contact with the L-shaped spacers, to obtain the source and drain having tilted faces.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 6, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas POSSEME
  • Publication number: 20200227271
    Abstract: A method is provided for etching a dielectric layer disposed on at least one layer based on gallium nitride (GaN), the dielectric layer being formed by a material based on one from SixNy and SixOy, the method including: first etching of the dielectric layer on only part of a thickness to define therein a partial opening and a residual portion situated in line with the opening and having another thickness; implanting ions in line with the opening over a thickness greater than the another thickness to modify a material of the dielectric layer over an entire thickness of the residual portion, and modify a material of the base layer of GaN; removing the residual portion by a second etching, selective of the modified dielectric layer with respect to the nonmodified material and with respect to the modified layer based on GaN; and annealing of the layer based on GaN.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 16, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas POSSEME, Frederic LE ROUX
  • Publication number: 20200211906
    Abstract: A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.
    Type: Application
    Filed: December 12, 2019
    Publication date: July 2, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Cyrille LE ROYER
  • Publication number: 20200203161
    Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas POSSEME, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
  • Publication number: 20200185497
    Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.
    Type: Application
    Filed: November 29, 2019
    Publication date: June 11, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, Fabrice NEMOUCHI