Patents by Inventor Nicolas POSSEME

Nicolas POSSEME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362181
    Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: June 14, 2022
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, Fabrice Nemouchi
  • Publication number: 20220172959
    Abstract: A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 2, 2022
    Inventors: Olivier POLLET, Laurent GRENOUILLET, Nicolas POSSEME
  • Publication number: 20220172093
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Publication number: 20220173163
    Abstract: A method for increasing the surface roughness of a layer based on a metal having a catalytic power, includes fixing fluorine or chlorine on the surface of the metal based layer, by exposing the metal based layer to a plasma formed from a reactive gas containing fluorine or chlorine; exposing the surface of the metal based layer to a humid environment to produce an acid, by reaction of hydrogen from the humid environment with the fluorine or the chlorine fixed on the surface of the metal based layer, the acid reacting with the metal to form residues, the whole of the residues forming a pattern on the surface of the metal based layer, and etching the metal based layer through the residues, so as to transfer the pattern into the metal based layer.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Inventors: Nicolas POSSEME, Laurent GRENOUILLET, Olivier POLLET
  • Publication number: 20220173229
    Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Publication number: 20220068724
    Abstract: A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 3, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Fabrice NEMOUCHI, Clemens FITZ, Nicolas POSSEME
  • Publication number: 20220068653
    Abstract: A method for etching at least one portion of a III-N material layer, including the implementation of the following steps of: a) first etching of a first part of the thickness of the portion of the III-N material layer, implemented by using a first plasma including chlorine; b) exposing at least one part of a remaining thickness of the portion of the III-N material layer to a second plasma including helium or hydrogen; c) chlorinating the part of the remaining thickness of the portion of the III-N material layer, transforming the part of the remaining thickness of the portion of the III-N material layer into a chlorinated material layer; d) second etching of the chlorinated material layer, implemented by using a third plasma including argon.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 3, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Simon RUEL
  • Patent number: 11244868
    Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: February 8, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Publication number: 20220028803
    Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a level of interconnections (30A) comprising vias (30), the method comprising the following steps: providing the first level (10A) and a dielectric layer (200, 201, 202), making a hard metal mask (300) on the dielectric layer (200, 201, 202), etching the dielectric layer (200, 201, 202) through the mask openings (301) by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask (300) by hydrolysis so as to form randomly distributed residues (31) at certain openings (320R), filling the openings (320, 320R) so as to form at least the vias (30) of the level of interconnections (30A), said vias (30) comprising functional vias (30OK) at the openings without residues (320) and inactive vias (30KO) at the openings with residues (320R).
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Stefan LANDIS
  • Publication number: 20220028802
    Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress ?r on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thickn
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Stefan LANDIS, Hubert TEYSSEDRE
  • Patent number: 11227936
    Abstract: There is provided a method for producing a transistor with a raised source and drain the method including depositing a layer on the gate pattern and the active layer; carrying out an isotropic modification of the layer over a thickness to obtain a first portion of modified layer, carrying out an anisotropic modification of the layer over another thickness, along a direction normal to the active layer, to obtain second portions of modified layer, by conserving portions of non-modified layer on the flanks of the gate pattern and at the foot of the gate pattern, removing the first and second modified portions by conserving the portions, by selective etching, to form spacers having an L-shape, epitaxially growing the source and drain in contact with the L-shaped spacers, to obtain the source and drain having tilted faces.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 18, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 11217446
    Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 4, 2022
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Posseme, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
  • Patent number: 11164752
    Abstract: A method is provided for etching a dielectric layer disposed on at least one layer based on gallium nitride (GaN), the dielectric layer being formed by a material based on one from SixNy and SixOy, the method including: first etching of the dielectric layer on only part of a thickness to define therein a partial opening and a residual portion situated in line with the opening and having another thickness; implanting ions in line with the opening over a thickness greater than the another thickness to modify a material of the dielectric layer over an entire thickness of the residual portion, and modify a material of the base layer of GaN; removing the residual portion by a second etching, selective of the modified dielectric layer with respect to the nonmodified material and with respect to the modified layer based on GaN; and annealing of the layer based on GaN.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 2, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Posseme, Frederic Le Roux
  • Patent number: 11127835
    Abstract: There is provided a method for etching a dielectric layer covering at least partially a flank of a structure made of a semi-conductive material, the structure having at least one face, the method including a plurality of sequences, each including at least the following steps: a main oxidation so as to form an oxide film; a main anisotropic etching of the oxide film, carried out so as to etch a portion of the oxide film extending parallel to the flanks and at least some of the dielectric layer, be stopped before etching the structure and a whole thickness of another portion of the oxide film extending perpendicularly to the flanks, the steps being repeated until the complete removal of the dielectric layer located on the flanks of the structure.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 21, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Posseme, Vincent Ah-Leung, Olivier Pollet
  • Patent number: 11121043
    Abstract: There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 14, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Cyrille Le Royer, Yves Morand
  • Patent number: 11081399
    Abstract: A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 3, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Cyrille Le Royer
  • Patent number: 11049724
    Abstract: A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ?1 less than a resistivity ?2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 29, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lamia Nouri, Frederic-Xavier Gaillard, Stefan Landis, Nicolas Posseme
  • Publication number: 20210090880
    Abstract: A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 25, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Frédéric LE ROUX
  • Publication number: 20210066133
    Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.
    Type: Application
    Filed: August 10, 2020
    Publication date: March 4, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Cyrille LE ROYER, Fabrice NEMOUCHI
  • Publication number: 20210057283
    Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 25, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas POSSEME