Abstract: A method for etching at least a portion of a layer based on a III-N material includes exposing a least one portion of an upper face of the III-N layer to a plasma treatment with bias voltage pulsing based on chlorine, wherein the plasma treatment is configured to present a duty cycle comprised between 20% and 80%. A first non-zero polarization bias is applied to the substrate during Ton, and a second polarization bias lesser than the first non-zero polarization bias or no polarization bias is applied, during Toff, so as to etch the portion of the III-N layer. The duration of the etching is significantly reduced to obtain a satisfying quality of the III-N layer for the operation of a microelectronic device, such as a transistor or a diode.

Abstract: A method for manufacturing a three-dimensional structure comprising supplying a stack comprising, stacked in a vertical direction, a support substrate, a sacrificial layer, a layer of interest having a sidewall and a tensor layer having a sidewall, the tensor layer having a residual stress. The method also comprises removing a removal portion of the sacrificial layer, while retaining a remaining portion of the sacrificial layer underlying the layer of interest. The removal portion is located in line with a lateral portion of the layer of interest extending from the entire sidewall of the layer of interest. The residual stress of the tensor layer is configured to cause bending of the layer of interest during the step of removing the removal portion.

Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of: making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer; implanting dopants in second regions adjacent to the first region; depositing a protective dielectric layer covering the protective dielectric portion and the second regions; exposing the protective dielectric layer to a laser pulse; and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.

Abstract: A method for manufacturing a mould for nanoprinting and the associated mould, includes providing a substrate having a layer, and at least one ion implantation configured so as to obtain in the layer, at least one first non-implanted portion or portion having a first implantation, at least one second portion having a second implantation, and a third non-implanted portion distinct from the first portion. After implantation, the method includes etching the layer configured so as to have a different etching speed between at least the second portion and the third portion, so as to etch through the openings of an etching mask, a plurality of patterns of different heights being included in the layer.

Abstract: The invention is based on a method for producing an individualisation zone of a chip comprising a component level and a contact level comprising vias, the method comprising the following steps: providing the components level and a dielectric layer, forming a mask on the dielectric layer, etching the dielectric layer through mask openings so as to form openings opening onto the contact zones of the components level, forming fluorinated residue by inputting fluorinated species on at least some contact zones, the openings thus comprising openings with fluorinated residue and openings without residue, filling the openings so as to form the vias of the contact level, said vias comprising functional vias at the openings without residue and altered vias at the openings with residue.

Abstract: A method for producing a layer covering the first surfaces of a structure and leaving the second surfaces uncovered including a sequence for forming an initial layer by PEALD deposition, the sequence including cycles, each including injections of first and second precursor in a reaction chamber, and plasma formation in the reaction chamber. The cycles are carried out at a temperature Tcycle such that Tcycle ? (Tmin - 20° C.), Tmin being the minimum temperature of a nominal temperature window for a PEALD deposition. The method includes exposing the initial layer to a densification plasma such that the exposure to the ion flow makes the material on the first surfaces more resistant to etching than the material on the second surfaces. The method also includes a selective etching step, such that the initial layer covers the first surfaces of the front face of the structure by leaving the second surfaces uncovered.

Abstract: The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising: a) a first substrate, which carries at least one first line of a first superconducting material; b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via; c) at least one second line above said first via and in contact with the latter.

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, and before or after the provision of the structure, a deposition in the reaction chamber of a layer based on a material of chemical formula CxHyFz, at least x and z being non-zero. The method further includes a treatment, in the presence of the structure, of the layer based on a material of chemical formula CxHyFz by an activation plasma based on at least one from among oxygen and nitrogen. The treatment by the activation plasma is configured to consume at least partially the layer based on the material of chemical formula CxHyFz so as to activate the exposed layer of the structure.

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, a deposition of a layer based on a material of formula SiaYbXc, with X chosen from among fluorine F and chlorine Cl, and Y chosen from among oxygen O and nitrogen N, a, b and c being non-zero positive integers, a treatment of the layer SiaYbXc by an activation plasma based on at least one from among oxygen and nitrogen, the parameters of the deposition of the layer SiaYbXc being chosen so as to obtain a sufficiently low material density such that the layer SiaYbXc is at least partially consumed by the activation plasma.

Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.

Abstract: A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and h2/e=a2 and h1/e=a1<alim where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Abstract: A process for producing a hybrid structured surface, including depositing, on a substrate, a layer of mineral resin including a proportion of Si and/or of SiO2 includes between 1% and 30% by molar mass; forming a structure including a plurality of pattern motifs in that layer, having at least one dimension, measured parallel or perpendicular to the substrate, includes between 50 nm and 500 ?m; forming a roughness on at least part of the surface of the pattern motifs.

Abstract: A method for forming spacers of a gate of a transistor is provided, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions, and basal portions covering the active layer; anisotropically modifying the basal portions by implantation of hydrogen-based ions in a direction parallel to the lateral sides of the gate, forming modified basal portions; annealing desorbing the hydrogen from the active layer and transforming the modified basal portions into second modified basal portions; and removing the modified basal portions by selective etching of the modified dielectric material with respect to the non-modified dielectric material and with respect to the semiconductive material, so as to form the spacers on the lateral sides of the gate.

Abstract: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies ?i (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

Abstract: A method is provided for etching a dielectric layer covering a top and a flank of a three-dimensional structure, the method including: a first etching of the dielectric layer, including: a first fluorine-based compound and oxygen, the first etching being performed to: form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and the second etchings being repeated until removing the dielectric layer located on the flank of the structure, and before deposition of the dielectric layer, a formation of an intermediate protective layer between the top and the dielectric layer.

Abstract: A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

Abstract: A semiconductor device includes a substrate; a plurality of gate stacks situated horizontally following one another on the substrate, each gate stack including a layer of a dielectric material in contact with the substrate and a layer of a conductive material on the layer of dielectric material; a source and a drain situated on the substrate on either side of the plurality of gate stacks; a plurality of first spacers made of a first dielectric material, called secondary spacers, having a first width, called width of the secondary spacers, the source and the drain being separated from the closest gate stack by a secondary spacer; at least one main spacer made of a second dielectric material, a main spacer being situated between each gate stack, the width of the main spacer(s) being greater than the width of the secondary spacers.

Abstract: A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.

Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.