Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of: making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer; implanting dopants in second regions adjacent to the first region; depositing a protective dielectric layer covering the protective dielectric portion and the second regions; exposing the protective dielectric layer to a laser pulse; and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.

Abstract: A method for manufacturing a mould for nanoprinting and the associated mould, includes providing a substrate having a layer, and at least one ion implantation configured so as to obtain in the layer, at least one first non-implanted portion or portion having a first implantation, at least one second portion having a second implantation, and a third non-implanted portion distinct from the first portion. After implantation, the method includes etching the layer configured so as to have a different etching speed between at least the second portion and the third portion, so as to etch through the openings of an etching mask, a plurality of patterns of different heights being included in the layer.

Abstract: A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.

Abstract: A method for making an individualization zone of a microchip comprising a first level and a second level of electrical tracks, and a level of interconnections comprising vias. The method includes: providing the first level and a dielectric layer, making a hard metal mask on the dielectric layer, etching the dielectric layer through the mask openings by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask by hydrolysis so as to form randomly distributed residues at certain openings, and filling the openings so as to form at least the vias of the level of interconnections, the vias comprising functional vias at the openings without residues and inactive vias at the openings with residues.

Abstract: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies ?i (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Abstract: A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

Abstract: The invention is based on a method for producing an individualisation zone of a chip comprising a component level and a contact level comprising vias, the method comprising the following steps: providing the components level and a dielectric layer, forming a mask on the dielectric layer, etching the dielectric layer through mask openings so as to form openings opening onto the contact zones of the components level, forming fluorinated residue by inputting fluorinated species on at least some contact zones, the openings thus comprising openings with fluorinated residue and openings without residue, filling the openings so as to form the vias of the contact level, said vias comprising functional vias at the openings without residue and altered vias at the openings with residue.

Abstract: The present description concerns an optoelectronic device manufacturing method, comprising the following steps: forming, on the upper surface side of a first substrate (100), a plurality of LEDs (101), each formed of a three-dimensional semiconductor element; depositing, on the upper surface side of the first substrate, a first layer (205a) made of a first material different from silicon oxide, said first layer (205a) laterally surrounding and covering the LEDs (101) and having a planar upper surface; and depositing a second layer (205b) made of silicon oxide on the upper surface of the first layer (205a), wherein the first material is such that the first layer (205a) is selectively etchable over the LEDs (101) and that the second layer (205b) is selectively etchable over the first layer.

Abstract: A method for producing a layer covering the first surfaces of a structure and leaving the second surfaces uncovered including a sequence for forming an initial layer by PEALD deposition, the sequence including cycles, each including injections of first and second precursor in a reaction chamber, and plasma formation in the reaction chamber. The cycles are carried out at a temperature Tcycle such that Tcycle ? (Tmin - 20° C.), Tmin being the minimum temperature of a nominal temperature window for a PEALD deposition. The method includes exposing the initial layer to a densification plasma such that the exposure to the ion flow makes the material on the first surfaces more resistant to etching than the material on the second surfaces. The method also includes a selective etching step, such that the initial layer covers the first surfaces of the front face of the structure by leaving the second surfaces uncovered.

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, a deposition of a layer based on a material of formula SiaYbXc, with X chosen from among fluorine F and chlorine Cl, and Y chosen from among oxygen O and nitrogen N, a, b and c being non-zero positive integers, a treatment of the layer SiaYbXc by an activation plasma based on at least one from among oxygen and nitrogen, the parameters of the deposition of the layer SiaYbXc being chosen so as to obtain a sufficiently low material density such that the layer SiaYbXc is at least partially consumed by the activation plasma.

Abstract: The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising: a) a first substrate, which carries at least one first line of a first superconducting material; b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via; c) at least one second line above said first via and in contact with the latter.

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, and before or after the provision of the structure, a deposition in the reaction chamber of a layer based on a material of chemical formula CxHyFz, at least x and z being non-zero. The method further includes a treatment, in the presence of the structure, of the layer based on a material of chemical formula CxHyFz by an activation plasma based on at least one from among oxygen and nitrogen. The treatment by the activation plasma is configured to consume at least partially the layer based on the material of chemical formula CxHyFz so as to activate the exposed layer of the structure.

Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.

Abstract: A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and h2/e=a2 and h1/e=a1<alim where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Abstract: A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.

Abstract: A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.

Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained

Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

Abstract: A process for producing a hybrid structured surface, including depositing, on a substrate, a layer of mineral resin including a proportion of Si and/or of SiO2 includes between 1% and 30% by molar mass; forming a structure including a plurality of pattern motifs in that layer, having at least one dimension, measured parallel or perpendicular to the substrate, includes between 50 nm and 500 ?m; forming a roughness on at least part of the surface of the pattern motifs.