Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

Abstract: A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ?1 less than a resistivity ?2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.

Abstract: A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiwCl(2w+2) and SiwF(2w+2), w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.

Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns

Abstract: A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.

Abstract: A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.

Abstract: A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.

Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).

Abstract: A method for forming a functionalised guide pattern for the self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern made of a first material having a first chemical affinity for the block copolymer, the guide pattern having a cavity with a bottom and side walls; grafting a functionalisation layer made of a second polymeric material having a second chemical affinity for the block copolymer, the functionalisation layer having a first portion grafted onto the bottom of the cavity and a second portion grafted onto the side walls of the cavity; selectively etching the second portion of the functionalisation layer relative to the first portion of the functionalisation layer, the etching including a step of exposure to an ion beam following a direction that intersects the second portion of the functionalisation layer, such that the ion beam does not reach the first portion of the functionalisation layer.

Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.

Abstract: A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer.

Abstract: The invention concerns a support intended for the implementation of a method of self-assembly of at least one element on a surface of the support, including at least one assembly pad on said surface, a liquid drop having a static angle of contact on the assembly pad smaller than or equal to 15°, and nanometer- or micrometer-range pillars on said surface around the pad, the liquid drop having a static angle of contact on the pillars greater than or equal to 150°.

Abstract: A process for producing conductive connections to an electronic chip, comprising the following steps: a) depositing an insulating layer on one face of a wafer; b) producing a layer based on at least one metal covering the insulating layer and equipped with first apertures; c) etching second apertures in the insulating layer in the extension of the first apertures by plasma etching in a plasma based on at least one halogen-containing compound; d) vacuum annealing the entire structure obtained after step c); and e) forming, after step d), the conductive connections in the second apertures.

Abstract: There is provided a method for producing, on one same plate, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a plate including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

Abstract: A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiwCl(2w+2) and SiwF(2w+2), w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.

Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least: a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411?, 411?) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step; c) a step of removing (461, 462) the modified zones (411

Abstract: A method for producing patterns in a layer to be etched, from a stack including at least the layer to be etched and a masking layer overlying the layer to be etched, with the masking layer having at least one pattern. The method includes modifying a first area of the layer to be etched by ion implantation through the masking layer; depositing a buffer layer to cover the pattern of the masking layer; modifying another area of the layer to be etched, different from the first area, by ion implantation through the buffer layer, to a depth of the layer to be etched greater than the implantation depth of the preceding step of modifying; removing the buffer layer; removing the masking layer; removing the modified areas by etching them selectively to the non-modified areas of the layer to be etched.

Abstract: A method for etching a layer of assembled block copolymer including first and second polymer phases, the etching method including a first step of etching by a first plasma formed from carbon monoxide or a first gas mixture including a fluorocarbon gas and a depolymerising gas, the first etching step being carried out so as to partially etch the first polymer phase and to deposit a carbon layer on the second polymer phase, and a second step of etching by a second plasma formed from a second gas mixture including a depolymerising gas and a gas selected among the carbon oxides and the fluorocarbon gases, the second etching step being carried out so as to etch the first polymer phase and the carbon layer on the second polymer phase.

Abstract: The invention relates to aA process for producing conductive connections to an electronic chip, comprising the following steps: a) depositing an insulating layer on one face of a wafer; b) producing a layer based on at least one metal covering the insulating layer and equipped with first apertures; c) etching second apertures in the insulating layer in the extension of the first apertures by plasma etching in a plasma based on at least one halogen-containing compound; d) vacuum annealing the entire structure obtained after step c); and e) forming, after step d), the conductive connections in the second apertures.