Patents by Inventor Nicolas Sassiat
Nicolas Sassiat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886419Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.Type: GrantFiled: March 6, 2018Date of Patent: January 5, 2021Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Publication number: 20180198000Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Patent number: 9960284Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.Type: GrantFiled: October 30, 2015Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Publication number: 20170330970Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
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Patent number: 9812573Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.Type: GrantFiled: May 13, 2016Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
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Publication number: 20170125610Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Alexandru Romanescu, Christian Schippel, Nicolas Sassiat
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Patent number: 9620589Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.Type: GrantFiled: April 7, 2014Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Nicolas Sassiat, Ran Yan, Kun-Hsien Lin, Jan Hoentschel
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Patent number: 9460955Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.Type: GrantFiled: November 27, 2013Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Ran Yan, Nicolas Sassiat, Alban Zaka, Kun-Hsien Lin
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Patent number: 9396950Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.Type: GrantFiled: February 20, 2014Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Nicolas Sassiat, Jan Hoentschel, Torben Balzer, Alban Zaka
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Patent number: 9263270Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.Type: GrantFiled: June 6, 2013Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Alban Zaka, Ran Yan, Nicolas Sassiat, El Mehdi Bazizi, Jan Hoentschel
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Patent number: 9231045Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.Type: GrantFiled: April 30, 2013Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Jan Hoentschel, Stefan Flachowsky, Nicolas Sassiat, Ralf Richter
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Publication number: 20150287782Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Nicolas Sassiat, Ran Yan, Kun-Hsien Lin, Jan Hoentschel
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Patent number: 9136266Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.Type: GrantFiled: July 16, 2013Date of Patent: September 15, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Ran Yan, Nicolas Sassiat, Jan Hoentschel, Torben Balzer
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Publication number: 20150145000Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Ran Yan, Nicolas Sassiat, Alban Zaka, Kun-Hsien Lin
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Patent number: 9029214Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.Type: GrantFiled: January 14, 2013Date of Patent: May 12, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Jan Hoentschel, Stefan Flachowsky, Nicolas Sassiat, Ran Yan
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Patent number: 8999803Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a fluorine implant region in the halo region of the first active region before or after formation of the drain and source extension and halo regions.Type: GrantFiled: May 31, 2013Date of Patent: April 7, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Nicolas Sassiat, Shiang Yang Ong, Ran Yan, Torben Balzer
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Publication number: 20150076618Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.Type: ApplicationFiled: September 19, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Ran Yan, Nicolas Sassiat, Ralf Richter, Jan Hoentschel
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Patent number: 8951877Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.Type: GrantFiled: March 13, 2013Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Nicolas Sassiat, Carsten Grass, Jan Hoentschel, Ran Yan, Ralf Richter
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Publication number: 20150021703Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.Type: ApplicationFiled: July 16, 2013Publication date: January 22, 2015Inventors: Ran Yan, Nicolas Sassiat, Jan Hoentschel, Torben Balzer
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Publication number: 20140361385Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.Type: ApplicationFiled: June 6, 2013Publication date: December 11, 2014Inventors: Alban Zaka, Ran Yan, Nicolas Sassiat, El Mehdi Bazizi, Jan Hoentschel