INTEGRATED CIRCUITS WITH A CORRUGATED GATE, AND METHODS FOR PRODUCING THE SAME
Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.
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The technical field generally relates to integrated circuits and methods for producing integrated circuits, and more particularly relates to integrated circuits with transistors having corrugations in the transistor gate and channel and methods for producing the same.
BACKGROUNDTransistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel and that is separated from the channel by a gate dielectric structure. The channel length extends from the source to the drain, and the channel width runs perpendicular to the length.
The amount of current that passes through a field effect transistor (FET) in the “on” state depends, in part, on the width of a channel positioned under a gate of the FET. The “on” current is given by the formula Ion≈μ*Cox*Wsi/Lg*(Vdd−Vth)2, where Ion is the “on” current, μ is the carrier mobility, Cox is the gate oxide capacitance, Wsi is the gate width, Lg is the gate length, Vdd is the drain voltage, and Vth is the threshold voltage. As can be seen, an increase in the width of the channel (Wsi) results in a larger “on” current. While higher “on” currents are desirable for many applications, there is pressure to reduce the size of integrated circuits and the electronic components, such as transistors, used in those integrated circuits. Thus, simply increasing the width of the gate to increase the “on” current is not desirable.
Accordingly, it is desirable to provide systems and methods for producing a FET with an increased channel width. In addition, it is desirable to provide a FET with higher “on” current values without utilizing more of the substrate surface area. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
BRIEF SUMMARYA method is provided for producing an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.
In a different embodiment, a method is provided for producing an integrated circuit. The method includes forming a gate insulator overlying a substrate, and forming a gate overlying the gate insulator. The gate is formed to include a gate corrugation on a gate bottom surface, and the gate corrugation increases an effective gate width. A source and a drain are formed on opposite sides of the gate insulator.
An apparatus is provided for an integrated circuit. The integrated circuit includes a substrate with a source and a drain. A gate overlies the substrate between the source and drain, and the gate has a gate bottom surface. The gate bottom surface includes a corrugation.
The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
As noted above, the “on” current of a FET is directly related to the channel width. Various embodiments of FETs contemplated herein utilize corrugated channels to increase the “on” current of the FETS. Corrugations increase the effective width of a channel and without increasing other dimensions of the channel or gate. In this regard, corrugations increase the “on” current of a FET for a fixed gate size. The corrugations increase the effective width of a channel in the same way that a crooked line between two points is longer than a straight line between the same two points.
An exploded view of an exemplary embodiment of a field effect transistor (FET) 10 is illustrated in
The substrate 18 includes a source 30 and a drain 32 positioned on opposite sides of the channel 16, so the source 30 and drain 32 are also on opposite sides of the gate insulator 14 and the gate 12. The channel 16 has a channel length 34, indicated by double headed arrows, extending from the source 30 to the drain 32, and a channel width 36, indicated by double headed arrows, perpendicular to the channel length 34. The gate 12 has a gate length 38, indicated by double headed arrows, and a gate width 40, indicated by double headed arrows, that correspond to the channel length 24 and the channel width 26. The gate corrugation 24, the channel corrugation 26, and the gate insulator corrugation 28 all extend along, or parallel to, the gate length 40 and the channel length 36, so the corrugations 24, 26, 28 run from the source 30 to the drain 32.
In an exemplary embodiment, the source 30 has a source surface 42 that is planar, and the drain 32 has a drain surface 44 that is planar. The source surface 42 and the drain surface 44 are the upper, exposed portions of the source 30 and drain 32, respectively, which are also a portion of a substrate surface 48. In other embodiments, the channel corrugation 26 can continue and extend through the source 30 and/or the drain 32, as well as the substrate 18 beyond the source 30 and drain 32. The substrate 18 is generally horizontal, so the source 30, drain 32, and channel 16 are generally horizontal as well. The substrate 18 has a substrate surface 48 that can include corrugations, so the substrate surface 48 may not be completely flat. However, in an exemplary embodiment, the substrate surface 48 extends in a generally horizontal direction from the source surface 42 and the drain surface 44.
Reference is now made to an exemplary embodiment shown in
Many different types and styles of gate corrugations 24 are possible, and the different types and styles of gate corrugations 24 are matched by the channel corrugations 26 and the gate insulator corrugations 28. For example, the exemplary embodiment in
Reference is now made again to
An exemplary embodiment for manufacturing a FET 10 begins with reference to
Reference is now made to the exemplary embodiment illustrated in
Reference is now made to an exemplary embodiment illustrated in
Reference is now made to the embodiment shown in
Reference is now made to an exemplary embodiment illustrated in
Reference is now made to
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.
Claims
1. An integrated circuit comprising:
- a substrate;
- a source within the substrate;
- a drain within the substrate; and
- a gate overlying the substrate between the source and the drain, wherein the gate comprises a gate bottom surface, and wherein the gate bottom surface comprises a gate corrugation.
2. The integrated circuit of claim 1 further comprising a gate insulator, wherein the gate overlies the gate insulator, and wherein the gate insulator comprises a gate insulator corrugation aligned with the gate corrugation.
3. The integrated circuit of claim 1 further comprising a channel positioned within the substrate between the source and the drain, wherein the channel further comprises a channel corrugation aligned with the gate corrugation.
4. The integrated circuit of claim 3 wherein the channel corrugation extends through the source and the drain.
5. The integrated circuit of claim 1 wherein the source comprises a source surface that is planar, and the drain comprises a drain surface that is planar.
6. The integrated circuit of claim 1 wherein the gate has a gate length extending from the source to the drain, and the gate corrugation extends parallel with the gate length.
7. The integrated circuit of claim 1 wherein the source comprises a source surface, the drain comprises a drain surface, and the substrate comprises a substrate surface, and wherein the substrate surface extends horizontally from the source surface and the drain surface.
8. The integrated circuit of claim 1 wherein the gate corrugation comprises a curved shape.
9. The integrated circuit of claim 1 wherein the gate corrugation comprises an angled shape.
10. An integrated circuit comprising:
- a field effect transistor (FET) comprising a channel, a gate insulator overlying the channel, and a gate overlying the gate insulator; and
- wherein the channel comprises a channel top surface, and wherein the channel top surface comprises a channel corrugation.
11. The integrated circuit of claim 10 wherein the channel comprises a channel length, and wherein the channel corrugation extends parallel with the channel length.
12. The integrated circuit of claim 10 wherein the channel corrugation comprises a curved shape.
13. The integrated circuit of claim 10 wherein the channel corrugation comprises a crenulated shape.
14. The integrated circuit of claim 10 wherein an “on” current of the FET is increased by the channel corrugation.
15. The integrated circuit of claim 10 wherein the gate insulator comprises a gate insulator corrugation aligned with the channel corrugation.
16. The integrated circuit of claim 10 further comprising:
- a substrate comprising a substrate surface;
- a source positioned within the substrate, wherein the source comprises a source surface;
- a drain positioned within the substrate, wherein the drain comprises a drain surface;
- wherein the channel is positioned within the substrate between the source and the drain; and
- wherein the substrate surface extends horizontally from the source surface and the drain surface.
17. The integrated circuit of claim 16 wherein the source surface is planar and the drain surface is planar.
18. The integrated circuit of claim 10 wherein the channel corrugation comprises a plurality of channel corrugations.
19. The integrated circuit of claim 10 wherein the gate comprises a gate bottom surface, and wherein the gate bottom surface comprises a gate corrugation aligned with the channel corrugation.
20. A method of producing an integrated circuit comprising:
- forming a corrugation mask on a substrate;
- forming a corrugation on the substrate;
- removing the corrugation mask from the substrate;
- forming a gate insulator overlying the corrugation on the substrate; and forming a gate overlying the gate insulator.
Type: Application
Filed: Sep 19, 2013
Publication Date: Mar 19, 2015
Applicant: GLOBALFOUNDRIES, Inc. (Grand Cayman)
Inventors: Ran Yan (Dresden), Nicolas Sassiat (Dresden), Ralf Richter (Radebeul), Jan Hoentschel (Dresden)
Application Number: 14/031,361
International Classification: H01L 29/423 (20060101); H01L 29/10 (20060101); H01L 29/40 (20060101);