Abstract: A transmitter device arranged to encode a set of digital input data into a succession of modulated chirps, whereby said digital input data are encoded according to a Gray code into codewords (320, 321, 322) having a plurality of bits, and having an interleaver that distributes the bits (C00, . . . Cnn) of each codeword into a series of digital modulation values (S0, . . . S7), at different bit positions, and to synthesize a series of modulated chirps whose cyclical shifts are determined by the modulation values. A special frame structure is defined in order to ensure high robustness, and variable bit-rate flexibility.

Abstract: A gateway device having a baseband processor for processing a plurality signals carrying a digital information modulated in the form of chirp signal, the chirp signals being either base chirps, for which the frequency changes from an initial instant to a final instant according to a predetermined base chirp function or modulated chirps, whose instantaneous frequencies vary according to one of a plurality of a functions that differ from said base chirp function, characterized in that the gateway device is arranged for simultaneously demodulating a plurality of signals having received at a same frequency and exhibiting different bitrates.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked

Abstract: An inductor structure comprising: a first loop and a second loop; a first feed line connected to a first end of the first loop and a second feed line connected to a first end of the second loop, each of the first and second feed lines extending through an area circumscribed by one of the first and second loops; and a crossover section adjacent to the first end of the first loop and the first end of the second loop, the crossover section coupling the first loop to the second loop so as to cause current flowing from the first feed line to the second feed line to circulate around the first loop in a first rotational direction and around the second loop in a second rotational direction opposite to the first rotational direction.

Abstract: A transmitter device arranged to encode a set of digital input data into a succession of modulated chirps, whereby said digital input data are encoded according to a Gray code into codewords (320, 321, 322) having a plurality of bits, and having an interleaver that distributes the bits (C00, . . . Cnn) of each codeword into a series of digital modulation values (S0, . . . S7), at different bit positions, and to synthesize a series of modulated chirps whose cyclical shifts are determined by the modulation values. A special frame structure is defined in order to ensure high robustness, and variable bit-rate flexibility.

Abstract: A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.

Abstract: A signal receiver having a gain control circuit comprising: detection means configured to form a representation of the excess amplitude during a training period of a signal received by the receiver; a first gain stimulus generator configured to generate a first gain stimulus in dependence on the excess amplitude detected by the detection means during the training period; averaging means configured to estimate the average of the signal received by the receiver during the training period; a second gain stimulus generator configured to generate a second gain stimulus in dependence on the average estimated by the averaging means during the training period; and a gain control signal generator configured to generate a gain control signal for the receiver in dependence on the first gain stimulus and the second gain stimulus.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked

Abstract: A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.

Abstract: A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.

Abstract: A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.

Abstract: A filter for filtering a received signal to attenuate an interferer therein, the interferer having a component at an interferer frequency, and the filter comprising: an intermediate filter providing a passband and a stopband; a first frequency converter configured to form a first intermediate signal by frequency-shifting an input signal derived from the received signal such that a component of the input signal at the interferer frequency is shifted to a frequency in the passband of the intermediate filter, and to input the first intermediate signal to the intermediate filter so as to cause the first intermediate signal to be filtered by the intermediate filter to form a second intermediate signal; a second frequency converter configured to form a cancellation signal by frequency-shifting the second intermediate signal such that a component of the second intermediate signal in the passband of the intermediate filter is shifted to the interferer frequency; and a cancellation unit configured to cancel the cancel

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duratio

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duratio

Abstract: System for converting a radiofrequency signal SRX so as to recover encoded information carried by the signal SRX, includes generating elements arranged to generate a signal SLO, mixing elements (3) arranged to generate a signal SRX-LO by mixing the signal SRX with the signal SLO, an analog/digital converter arranged to convert the signal SRXLO into a digital signal SRX-LO-Num, a device generating an error correction digital signal SCor, the device being arranged so that the signal SCor reflects the phase gap between the phase of the signal SLO and a phase setpoint, the phase setpoint being the phase of an ideal signal S0, ideal for recovering the encoded information carried by the signal SRX, combining elements arranged to generate the signal S0?-Num by combining the signal SRX-LO-Num with the signal SCor. A system for converting a digital signal so as to send a radiofrequency analog signal carrying the information of the digital signal is also described.

Abstract: A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a delayed reference clock signal; a phase comparator (27) configured to generate a quantized signal indicative of the phase difference between the output signal and the delayed reference clock signal, an integrator (28) configured to integrate the quantized signal to form an integrated signal; a first feedback path (22) configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and a second feedback path (23) configured to adjust the delay applied by the delay cell (26) in dependence on the integrated signal.

Abstract: A current generator for a phase-locked loop arranged to generate an output signal having predetermined frequency-relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided, a comparison unit arranged to compare the feedback signal with the reference signal and output a first error signal indicative of the phase-difference between the feedback signal and the reference signal to the current generator and a loop filter arranged to filter a current signal output by the current generator to form a control signal for controlling the signal generator, the current generator being capable of receiving the first error signal and generating a current in dependence thereon, receiving a second error signal indicative of an error in the feedback signal caused by the v

Abstract: A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duratio

Abstract: A radio transmitter includes a transmitter circuit having a transmission output and being configured to generate at the transmission output a signal for transmission; a reference voltage circuit configured to generate a substantially temperature-invariant reference voltage; a reference signal circuit having a reference output and being configured to receive the substantially temperature-invariant voltage generated by the reference voltage circuit and to generate at the reference output an oscillating reference signal of an amplitude that is derived from the temperature-invariant reference voltage; an amplitude sensor having an input and being configured for sensing the amplitude of a signal at the input and generating a sensed amplitude signal indicative of the sensed amplitude; and control apparatus configured to control the radio transmitter to operate in each of: a) a first mode in which it causes the input of the amplitude sensor to be coupled to the reference output; and b) a second mode in which it caus

Abstract: A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensation signal in dependence on the output of the oscillator and a reference signal; a correlator configured to frequency correlate an interferer signal and the low frequency compensation signal, and in dependence on that correlation generate a correlation signal; and an adaptive filter configured to adapt the interferer signal in dependence on the correlation signal to output a high frequency compensation signal; and a summation unit configured to combine the low frequency compensation signal and the high frequency compensation signal to form a control signal to drive the input of the oscillator.