Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

Abstract: A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.

Abstract: A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

Abstract: A method of forming a phase change memory device is provided. The method includes depositing an electrode layer on a phase change material core, and forming a sacrificial layer on the electrode layer. The method further includes depositing a planarization layer on the sacrificial layer, and depositing an anti-reflective coating on the planarization layer. The method further includes forming a template on the anti-reflective coating, and removing a portion of the anti-reflective coating, a portion of the planarization layer, and a portion of the sacrificial layer to form a reduced height sacrificial layer and a sacrificial layer section beneath the planarization layer section. The method further includes removing the anti-reflective coating section and planarization layer section to expose the sacrificial layer section, and removing the reduced height sacrificial layer and a portion of the electrode layer to form a top electrode on the phase change material core.

Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: Techniques for modifying a mask fabrication process based the identification of an abnormality in a pattern of a fabricated lithography mask are disclosed including comparing a fabricated lithography mask to a lithography mask design where the fabricated lithography mask is fabricated based at least in part on the lithography mask design using a mask fabrication process. An abnormality in a pattern of the fabricated lithography mask relative to a corresponding one of the plurality of patterns in the lithography mask design is identified based at least in part on the comparison of the fabricated lithography mask to the lithography mask design. A calibrated mask model is generated based at least in part on the identified abnormality in the pattern of the fabricated lithography mask and the mask fabrication process is modified based at least in part on the calibrated mask model.

Abstract: A phase change material (“PCM”) device is described. A non-limiting example of the PCM device includes a bottom electrode including a low resistivity material and a PCM material over the bottom electrode. The PCM device has a top electrode over the PCM material.

Abstract: Techniques for modifying a mask fabrication process based the identification of an abnormality in a pattern of a fabricated lithography mask are disclosed including comparing a fabricated lithography mask to a lithography mask design where the fabricated lithography mask is fabricated based at least in part on the lithography mask design using a mask fabrication process. An abnormality in a pattern of the fabricated lithography mask relative to a corresponding one of the plurality of patterns in the lithography mask design is identified based at least in part on the comparison of the fabricated lithography mask to the lithography mask design. A calibrated mask model is generated based at least in part on the identified abnormality in the pattern of the fabricated lithography mask and the mask fabrication process is modified based at least in part on the calibrated mask model.

Abstract: A Phase-change-memory (PCM) cell and method of forming the PCM are provided. In an illustrative embodiment, a method of forming a PCM cell includes forming a first layer of a first germanium-antimony-tellurium (GST) type material over at least a portion of the bottom and sides of a pore through a dielectric layer of low dielectric material to a bottom electrode. The method also includes forming a second layer of a second GST type material over the first GST type material along the bottom and sides of the pore over the bottom electrode. The first GST type material is different from the second GST type material.

Abstract: A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

Abstract: A self-align metal contact for a phase control memory (PCM) element is provided that mitigates unwanted residual tantalum nitride (TaN) particles that would otherwise remain after patterning a TaN surface using an RIE process.

Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Abstract: Techniques regarding protecting a dielectric material during additive patterning of one or more phase change memories are provided. For example, one or more embodiments described herein can comprise a method, which can comprise forming a bi-layer adjacent a phase change memory element. The bi-layer can comprise a dielectric material and a capping material that can protect a thickness of the dielectric material during a patterning process.

Abstract: A method of forming a self-aligned phase change memory element is provided. A bottom electrode is formed on a landing pad of a phase change memory element. A layer of dielectric material over the bottom electrode and a via etched through the dielectric material to expose the bottom electrode. The via is lined with a GST phase change layer that is etched back from the top surface of the dielectric layer. The via is then filled with a nitride fill, at least of portion of which is etched back from the top surface of the dielectric layer. A top electrode metal is then deposited at the top of the via, wherein the top electrode material is coupled to the phase change material and nitride fill material.

Abstract: Techniques regarding protecting a dielectric material during additive patterning of one or more phase change memories are provided. For example, one or more embodiments described herein can comprise a method, which can comprise forming a bi-layer adjacent a phase change memory element. The bi-layer can comprise a dielectric material and a capping material that can protect a thickness of the dielectric material during a patterning process.

Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; and ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.