Patents by Inventor Nicole Thomas

Nicole Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12248630
    Abstract: A wearable computing device with bio-signal sensors and a feedback module provides an interactive mediated reality (“VR”) environment for a user. The bio-signal sensors receive bio-signal data (for example, brainwaves) from the user and include bio-signal sensors embedded in a display isolator, having a deformable surface, and having an electrode extendable to contact the user's skin. The wearable computing device further includes a processor to: present content in the VR environment via the feedback module; receive bio-signal data of the user from the bio-signal sensor; process the bio-signal data to determine user states of the user, including brain states, using a user profile; modify a parameter of the content in the VR environment in response to the user states of the user. The user receives feedback indicating the modification of the content via the feedback module.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: March 11, 2025
    Assignee: INTERAXON INC.
    Inventors: Christopher Allen Aimone, Samuel Thomas MacKenzie, Graeme Daniel Moffat, Hubert Jacob Banville, Nicole Hélène Proulx
  • Patent number: 12240782
    Abstract: A glass composition includes SiO2, Al2O3, B2O3, alkali metal oxides, alkaline earth oxides, TiO2, CeO2, Fe2O3, and is provides a yellow-colored glass article.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 4, 2025
    Assignee: CORNING INCORPORATED
    Inventors: Kaveh Adib, Xiaoju Guo, Sean Thomas Ralph Locker, Lina Ma, Nicole Taylor Wiles
  • Patent number: 12230635
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Ehren Mannebach, Cheng-Ying Huang, Marko Radosavljevic
  • Publication number: 20250033988
    Abstract: Preparation of capped metal oxide nanocrystals comprising a metal oxide shell that are photocatalytically and thermally stable and their dispersions in monomers, oligomers, and polymers, as well as the resulting formulations and nanocomposite films. These nanocrystals are highly monodisperse with nanocrystal size between 3-100 n. Resultant formulations incorporating these nanocrystals and a matrix material are highly stable and result in nanocomposites that have high refractive index, are highly transparent, have minimal to no change in absorption upon thermal or UV processing and are optically transparent in the visible wavelengths with very little or no scattering.
    Type: Application
    Filed: December 20, 2022
    Publication date: January 30, 2025
    Inventors: Robert J. WIACEK, Selina Thomas MONICKAM, Mohammad Sadegh YAZDANPARAST, Brian SZYCHOWSKI, Guoyi FU, Peter Christopher GUSCHL, Grace E.M. MCCLINTOCK, Lei ZHENG, Zehra Serpil Gonen WILLIAMS, Mohammadreza AMIRMOSHIRI, Nicole Joud TADROS
  • Patent number: 12183739
    Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
  • Publication number: 20240332389
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 3, 2024
    Inventors: Nicole THOMAS, Michael K. HARPER, Leonard P. GULER, Marko RADOSAVLJEVIC, Thoe MICHAELOS
  • Patent number: 12046652
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Michael K. Harper, Leonard P. Guler, Marko Radosavljevic, Thoe Michaelos
  • Publication number: 20240088153
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Nicole THOMAS, Ehren MANNEBACH, Cheng-Ying HUANG, Marko RADOSAVLJEVIC
  • Patent number: 11862636
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Ehren Mannebach, Cheng-Ying Huang, Marko Radosavljevic
  • Publication number: 20220262796
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 18, 2022
    Inventors: Nicole THOMAS, Ehren MANNEBACH, Cheng-Ying HUANG, Marko RADOSAVLJEVIC
  • Publication number: 20220199620
    Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
  • Patent number: 11348919
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Ehren Mannebach, Cheng-Ying Huang, Marko Radosavljevic
  • Patent number: 11241552
    Abstract: An oropharyngeal airway device includes an elongated hollow body having proximal and distal ends, and a collar secured to the proximal end of the elongated hollow body. The device also includes an aspiration tube and an adapter where the adapter has a first open end and an opposing second open end. The first and second open ends are each coupled to the aspiration tube. In addition, the device includes a delivery conduit coupled to the adapter and positioned within the elongated hollow body in order to deliver gas from a gas supply to the distal end of the elongated hollow body and into an airway of a patient. The device includes at least one fastener within the collar for removably securing the adapter to the collar.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 8, 2022
    Inventor: Nicole Thomas
  • Publication number: 20210408257
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Inventors: Nicole THOMAS, Michael K. HARPER, Leonard P. GULER, Marko RADOSAVLJEVIC, Thoe MICHAELOS
  • Publication number: 20210407997
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Inventors: Nicole THOMAS, Ehren MANNEBACH, Cheng-Ying HUANG, Marko RADOSAVLJEVIC
  • Patent number: 10899510
    Abstract: A vial assembly may include a vial having a body to hold a liquid material, and a neck extending from the body. The neck may include a multi-use surface configured to permit access to the liquid material. The vial assembly may include a cap to be received by the neck and to cover the multi-use surface. The cap may include a base having a first major surface, and a second major surface opposite of the first major surface, arms extending from the second major surface, and a rupturable reservoir of disinfectant material carried by the base between the first major surface and the second major surface. One or more of the first major surface and the second major surface may be flexible so as to rupture the rupturable reservoir when the cap is received by the neck.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 26, 2021
    Inventors: Nicole Thomas, Ashley Tilton
  • Publication number: 20200282164
    Abstract: An oropharyngeal airway device includes an elongated hollow body having proximal and distal ends, and a collar secured to the proximal end of the elongated hollow body. The device also includes an aspiration tube and an adapter where the adapter has a first open end and an opposing second open end. The first and second open ends are each coupled to the aspiration tube. In addition, the device includes a delivery conduit coupled to the adapter and positioned within the elongated hollow body in order to deliver gas from a gas supply to the distal end of the elongated hollow body and into an airway of a patient. The device includes at least one fastener within the collar for removably securing the adapter to the collar.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventor: Nicole THOMAS
  • Publication number: 20200122906
    Abstract: A vial assembly may include a vial having a body to hold a liquid material, and a neck extending from the body. The neck may include a multi-use surface configured to permit access to the liquid material. The vial assembly may include a cap to be received by the neck and to cover the multi-use surface. The cap may include a base having a first major surface, and a second major surface opposite of the first major surface, arms extending from the second major surface, and a rupturable reservoir of disinfectant material carried by the base between the first major surface and the second major surface. One or more of the first major surface and the second major surface may be flexible so as to rupture the rupturable reservoir when the cap is received by the neck.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: NICOLE THOMAS, ASHLEY TILTON
  • Publication number: 20170290400
    Abstract: An article of luggage that has a built in storage compartment with customizable departments, that includes a top portion having at least two side walls, a closeable top, a closed bottom having an exterior bottom surface and an interior top compartment. This article of luggage also includes an open bottom portion having at least two side walls, a closed top having an exterior top surface, a closed bottom an interior bottom compartment and at least one access opening into the interior bottom compartment, and a compartmentalized tray having a plurality of individual removable compartments. A removable tray positioned within the interior bottom portion having removable interconnected walls cooperating to define a plurality of individual storage compartments. A track system is included to attach the top portion to the bottom portion, where the track system has a first component and a second component that slidingly engage one another.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventor: Nicole Thomas
  • Patent number: D884150
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 12, 2020
    Inventor: Nicole Thomas