Abstract: The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.

Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.

Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.

Abstract: The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV.

Abstract: A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.

Abstract: A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.

Abstract: The present invention relates to a method of reducing needle-like defects generated on a wafer rim in an etching process, wherein the etching process using both a photoresist material and hardmask material as a mask. After removing the photoresist material and the hardmask material, said method comprising the steps of: (i) depositing the photoresist material on the wafer again; (ii) performing wafer edge exposure (WEE) to form a ring of the wafer edge; and (iii) performing dry etching to the exposed ring of wafer edge to remove the needle-like defects generated on the wafer edge.

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.

Abstract: A method for forming a gate structure is provided. The forming method includes steps of providing a semiconductor substrate; forming an insulation layer, a first gate conductor layer, a second gate conductor layer, and a masking layer on the semiconductor substrate; removing portions of the masking layer, the semiconductor substrate, and the first gate conductor layer to define the gate structure by etching; executing a cleaning process to the semiconductor with a specific cleaning agent for etching the second gate conductor layer, thereby removing portions of the second gate conductor layer in the gate structure; and performing a thermal treatment process to the semiconductor substrate and forming an insulation spacer on the side surface of the gate structure.

Abstract: A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each the deep trench capacitor construction having a collar construction and a conductor construction is provided. The method of forming a shallow trench includes steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions, which is not covered by the mask, so as to form a first depth trench, in which the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, in which the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.

Abstract: A method for controlling an etching depth in a semiconductor fabricating process is provided. The method includes steps of providing a substrate having a first reflecting region and a second reflecting region, illuminating the first reflecting region and the second reflecting region with a coherence light having a wavelength &lgr; to generate an interference, performing a first etching on the second reflecting region to generate a height difference between the first reflecting region and the second reflecting region, wherein the interference intensity is changed with the first etching, and performing a second etching on the second reflecting region for a specific period of time to make the etching depth as the height difference when the interference intensity is changed to a relative extreme value.

Abstract: A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; removing the photoresist layer in an asher using a combination of oxygen plasma and water vapor, the ratio of oxygen plasma and water vapor being less than one; and performing a wet strip on the metal interconnect structure.

Abstract: An etching gas having a good chemical property for silicon etch back is made by mixing a SF6 gas with a Cl2 gas. With addition of an inert gas, good chamber conditions are maintained during silicon etch back, and the etching selectivity for silicon to an etching stop layer is improved.

Abstract: A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Abstract: A method to fabricate bottle-shaped deep trench into a semiconductor substrate. After a neck profile is formed, the chlorine gas at a predetermined flow rate is added to the etching plasma gas composition, while the flow rates of the plasma gases are increased by about 30% by volume, to create an enlarged lower portion of the deep trench. Preferably, the neck portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 87:13:35 sccm. The enlarged lower portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 113±12:17±2:46±5 sccm, and Cl2 provided at a flow rate between 10 and 40 sccm. It was found that the width of the lower portion of the deep trench can be increased by 100% with minimum side effects such as polymer deposition in the plasma chamber, which could occur as result of substantially increased flow rate of HBr and/or NF3.

Abstract: A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.

Abstract: A method to fabricate bottle-shaped deep trench in a semiconductor substrate which mainly involves two substitute plasma etching steps from the conventional approach. After a neck profile is formed, instead of raising the plasma gas pressure while keeping the etching composition constant, as in the conventional approach, the plasma gas pressure is first maintained the same, then decreased substantially. On the other hand, the concentrations of HBr and NF.sub.3 are increased substantially in both new steps. The first substitute plasma etching step is conducted at a pressure of 100 mtorr an RF power of about 1,000 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 200:20:20. The second substitute plasma etching step is conducted at plasma gas pressure of 30 mtorr, an RF power of 600 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 150:13:20.