Patents by Inventor Nigel Cave
Nigel Cave has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024536Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.Type: GrantFiled: April 18, 2019Date of Patent: June 1, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adra Carr, Vimal Kamineni, Ruilong Xie, Andrew Greene, Nigel Cave, Veeraraghavan Basker
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Publication number: 20200335392Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Inventors: Adra Carr, Vimal Kamineni, Ruilong Xie, Andrew Greene, Nigel Cave, Veeraraghavan Basker
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Patent number: 10468300Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.Type: GrantFiled: July 5, 2017Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Andre Labonte, Lars Liebmann, Daniel Chanemougame, Chanro Park, Nigel Cave, Vimal Kamineni
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Publication number: 20190139830Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.Type: ApplicationFiled: November 3, 2017Publication date: May 9, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Ruilong XIE, Minoli K. PATHIRANE, Chanro PARK, Guillaume BOUCHE, Nigel CAVE, Mahender KUMAR, Min Gyu SUNG, Huang LIU, Hui ZANG
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Patent number: 10249728Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.Type: GrantFiled: April 18, 2018Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Chanemougame, Andre Labonte, Ruilong Xie, Lars Liebmann, Nigel Cave, Guillaume Bouche
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Patent number: 10249535Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.Type: GrantFiled: February 15, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Daniel Chanemougame, Lars Liebmann, Nigel Cave
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Patent number: 10236218Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The semiconductor device may comprise a PFET fin; an NFET fin; a first metal silicide around the NFET fin; a second metal silicide around the PFET fin; and a fill metal around the second metal silicide, above the PFET fin, and above the NFET fin. Methods of forming such devices are also disclosed.Type: GrantFiled: February 20, 2018Date of Patent: March 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Julien Frougier, Hiroaki Niimi, Nigel Cave, Xusheng Kevin Wu
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Patent number: 10211100Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.Type: GrantFiled: March 27, 2017Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Lars Liebmann, Nigel Cave, Andre Labonte, Nicholas LiCausi, Guillaume Bouche, Chanro Park
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Publication number: 20190013241Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.Type: ApplicationFiled: July 5, 2017Publication date: January 10, 2019Inventors: Ruilong Xie, Andre Labonte, Lars Liebmann, Daniel Chane, Chanro Park, Nigel Cave, Vimal Kamineni
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Publication number: 20180277430Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Ruilong Xie, Lars Liebmann, Nigel Cave, Andre Labonte, Nicholas LiCausi, Guillaume Bouche, Chanro Park
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Publication number: 20180240883Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.Type: ApplicationFiled: April 18, 2018Publication date: August 23, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: DANIEL CHANEMOUGAME, ANDRE LABONTE, RUILONG XIE, LARS LIEBMANN, NIGEL CAVE, GUILLAUME BOUCHE
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Publication number: 20180233412Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.Type: ApplicationFiled: February 15, 2017Publication date: August 16, 2018Inventors: Ruilong XIE, Daniel CHANEMOUGAME, Lars LIEBMANN, Nigel CAVE
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Publication number: 20180204927Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: DANIEL CHANEMOUGAME, ANDRE LABONTE, RUILONG XIE, LARS LIEBMANN, NIGEL CAVE, GUILLAUME BOUCHE
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Patent number: 10026824Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.Type: GrantFiled: January 18, 2017Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Chanemougame, Andre Labonte, Ruilong Xie, Lars Liebmann, Nigel Cave, Guillaume Bouche
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Patent number: 8741743Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.Type: GrantFiled: January 5, 2007Date of Patent: June 3, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
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Patent number: 7565639Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).Type: GrantFiled: January 4, 2007Date of Patent: July 21, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
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Patent number: 7470624Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.Type: GrantFiled: January 8, 2007Date of Patent: December 30, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
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Publication number: 20080168418Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
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Publication number: 20080168417Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
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Publication number: 20080166859Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis