Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure.

Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure.

Abstract: Structures for an extended-drain field-effect transistor and methods of forming an extended-drain field-effect transistor. A source region is coupled to a semiconductor layer, a drain region is coupled to the semiconductor layer, and a first gate structure is positioned over a channel region of the semiconductor layer. An extended drain region is positioned between the channel region and the drain region. The extended drain region includes a portion of the semiconductor layer between the first gate structure and the drain region. A second gate structure is arranged over the portion of the semiconductor layer.

Abstract: Structures for an extended-drain field-effect transistor and methods of forming an extended-drain field-effect transistor. A source region is coupled to a semiconductor layer, a drain region is coupled to the semiconductor layer, and a first gate structure is positioned over a channel region of the semiconductor layer. An extended drain region is positioned between the channel region and the drain region. The extended drain region includes a portion of the semiconductor layer between the first gate structure and the drain region. A second gate structure is arranged over the portion of the semiconductor layer.

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

Abstract: The disclosure provides integrated circuit (IC) layouts and methods to form the same. An IC layout may include two standard cells, with a well contact cell laterally between them. The well contact cell may include a single semiconductor region having the first doping type, an active bridge region within the single semiconductor region, extending continuously from the first active region of the first standard cell to the third active region of the second standard cell. A doped tap region within the single semiconductor region is laterally separated from the active bridge region. The doped tap region is laterally aligned with the second active region and the fourth active region.

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

Abstract: A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

Abstract: A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.

Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.