Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

Abstract: One illustrative device disclosed a floating gate capacitor located in and above a first region of an SOI substrate located on a first side of an isolation trench and a transistor device located in and above a second region of the SOI substrate that is on the opposite side of the isolation trench. The device also includes a control gate formed in the bulk semiconductor layer in the first region and a gate structure that extends across the isolation trench and above the first and second regions. A first portion of the gate structure is positioned above the first region and the control gate and a second portion of the gate structure is positioned above the second region, wherein the first portion of the gate structure constitutes a floating gate for the floating gate capacitor and the second portion of the gate structure constitutes a transistor gate structure for the transistor device.

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract: A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.