Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.