Patents by Inventor Nigel P. Smith

Nigel P. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110238365
    Abstract: An empirical diffraction based overlay (eDBO) measurement of an overlay error is produced using diffraction signals from a plurality of diffraction based alignment pads from an alignment target. The linearity of the overlay error is tested using the same diffraction signals or a different set of diffraction signals from diffraction based alignment pads. Wavelengths that do not have a linear response to overlay error may be excluded from the measurement error.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 29, 2011
    Applicant: NANOMETRICS INCORPORATED
    Inventors: Jie Li, Zhuan Liu, Silvio J. Rabello, Nigel P. Smith
  • Publication number: 20110193839
    Abstract: A level shifter for use in LCD display applications is provided which includes a group of separate channels each with a signal input and a signal output and with channel control circuitry supporting gate voltage shaping for improving image quality. The level shifter further has a number of flicker clock inputs. The channel control circuitry of each particular channel in the group comprises logic circuitry combining all of said flicker clock inputs with the signal input of the particular channel and signal inputs form other channels into a gate voltage shaping enable signal for the control circuitry of the particular channel. With this configuration it is possible to use the same level shifter IC with only one flicker clock signal for all phases, regardless of how many, without the need for an additional synchronization signal, or multiple flicker clock signals as is conventional.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 11, 2011
    Applicant: Texas Instruments Deutschland GmbH
    Inventors: Nigel P. Smith, Byoung-Suk Kim, Stefan Reithmaier
  • Publication number: 20110069314
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Publication number: 20110058170
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Application
    Filed: November 9, 2010
    Publication date: March 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Patent number: 7876439
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Patent number: 7808643
    Abstract: Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 5, 2010
    Assignee: Nanometrics Incorporated
    Inventors: Nigel P. Smith, Kevin E Heidrich
  • Publication number: 20090296075
    Abstract: An overlay error is determined using a diffraction based overlay target by generating a number of narrow band illumination beams that illuminate the overlay target. Each beam has a different range of wavelengths. Images of the overlay target are produced for each different range of wavelengths. An intensity value is then determined for each range of wavelengths. In an embodiment in which the overlay target includes a plurality of measurement pads, which may be illuminated and imaged simultaneously, an intensity value for each measurement pad in each image is determined. The intensity value may be determined statistically, such as by summing, finding the mean or median of the intensity values of pixels in the image. Spectra is then constructed using the determined intensity value, e.g., for each measurement pad. Using the constructed spectra, the overlay error may then be determined.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Applicant: Nanometrics Incorporated
    Inventors: Jiangtao Hu, Chandra Saru Saravanan, Silvio J. Rabello, Zhuan Liu, Nigel P. Smith
  • Publication number: 20090116014
    Abstract: Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined.
    Type: Application
    Filed: December 19, 2008
    Publication date: May 7, 2009
    Applicant: Nanometrics Incorporated
    Inventors: Nigel P. Smith, Kevin E. Heidrich
  • Patent number: 7474401
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: January 6, 2009
    Assignees: International Business Machines Corporation, Accent Optical Technologies
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Publication number: 20080259334
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Application
    Filed: June 23, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Patent number: 4737648
    Abstract: The invention comprises apparatus capable of unambiguous determination of the length and diameter of fibrous particles, especially asbestos fibres, based on near-forward scattering of light by fibres aligned in a hydrodynamically focused gas flow. Three portions of scattered light are detected, two portions perpendicular to the fibre axis and one aligned with it, from which length and diameter can be independently determined. This independence is achieved by allowing only selected parts of the light scattered within certain selected ranges of angles to reach each detector. A two-detector instrument capable of accurate determination of fibre diameter is also described.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: April 12, 1988
    Assignee: VG Instruments Group Limited
    Inventors: Nigel P. Smith, Neil A. Downie