Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: An electronic display may include a first anode configured to carry a red emission signal, a second anode configured to carry a blue emission signal, a third anode configured to carry a green emission signal, and a micro-driver configured to stagger a timing of the red emission signal, the blue emission signal, and the green emission signal based on an emission clock signal to display image content on the electronic display.

Abstract: Touch sensitive display technologies (e.g., integrated touch-display pixel-based systems) are evolving to contain more analog and digital circuits inside the panel itself instead of the traditionally simple thin-film transistors. This improves the display characteristics but makes those circuits more vulnerable to the impact of external ESD strikes, which can degrade the user experience. This disclosure describes a series of circuits and techniques to mitigate the impact of these discharges on front of screen artifacts and potential false touches. These circuits and techniques may include: performing configuration-only panel updates independently of the image refresh rate, improving the in-panel memory circuits to make them resistant to unexpected pin toggles via disabling of a write path in response to a read clock, implementing a pin corruption detector and implementing a supply injection detector.

Abstract: An electronic device may include an electronic display including display pixels to display an image based on compensated image data. As image data is written to a pixel in the row of pixels, capacitive coupling at a driver may lead to distortion on the driver. In particular, the capacitive coupling may cause distortion at a storage capacitor, which may lead to current droop at the pixel. The current droop may be reduced or eliminated in each pixel by performing pixel compensation. The pattern of the pixel compensation may be selected such that, over a number of subframes, an average amount of light is the same or similar to what would be emitted had pixel compensation been performed on each pixel in each subframe.

Abstract: A device includes a plurality of high voltage cells (HVC) coupled to a plurality of resistors, and a controller. The plurality of HVC generates an output voltage that is higher than an input voltage to the plurality of HVC. The controller receives a reference voltage and an output voltage from a resistor of the plurality of resistors. The controller generates a signal responsive to a difference between the reference voltage and the output voltage. The controller forms a closed feedback loop with the plurality of HVC and the plurality of resistors. The generated signal is input to the plurality of HVC. A substrate of a resistor of the plurality of resistors is biased to an output of at least one high voltage cell of the plurality of HVC. Output of the at least one high voltage cell is input to another high voltage cell.

Abstract: A device includes a plurality of high voltage cells (HVC) coupled to a plurality of resistors, and a controller. The plurality of HVC generates an output voltage that is higher than an input voltage to the plurality of HVC. The controller receives a reference voltage and an output voltage from a resistor of the plurality of resistors. The controller generates a signal responsive to a difference between the reference voltage and the output voltage. The controller forms a closed feedback loop with the plurality of HVC and the plurality of resistors. The generated signal is input to the plurality of HVC. A substrate of a resistor of the plurality of resistors is biased to an output of at least one high voltage cell of the plurality of HVC. Output of the at least one high voltage cell is input to another high voltage cell.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.