Abstract: Techniques are disclosed for enhancing the speed at which pixel levels are read out and sampled for processing. A method of processing pixel levels includes clamping a pixel readout line to a voltage level less than a voltage corresponding to a signal sensed by an n-MOS pixel. Subsequently, the pixel readout line is coupled to an output of an n-MOS source-follower and the pixel signal is read out onto the pixel readout line through the n-MOS source-follower. The pixel signal that was read out is passed through a p-MOS source-follower to a processing circuit. Before passing the pixel signal through the p-MOS source-follower to the processing circuit, a capacitive storage node in the processing circuit is clamped to a voltage greater than a signal at an input to the p-MOS source-follower. Subsequently, an output of the p-MOS source-follower is coupled to the processing circuit, and a signal corresponding to the pixel signal is stored by the processing circuit.

Abstract: An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a differential amplifier. In operation, both pixels are reset at the same time, causing differential reset signals to be output from the amplifier. The charge from the first pixel is readout and a differential pixel signal for the first pixel is output from the amplifier. Because the reset and pixel signals are differential signals generated within the pixels, they are free from common-mode noise. Correlated double sampling can be used to obtain the pixel output value, which is also free from common-mode noise, from the differential reset and pixel signals. The second pixel may be readout in the same manner. Because the two pixels are sharing circuitry, the pixels have decreased fill factor and complexity as well.

Abstract: Imaging sensors having dual-port for digital readout to pipeline readout processes of two different groups of pixels.

Abstract: Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned simultaneously. Pixels in an element are located in a plurality of rows and columns. In exemplary embodiments, pixel voltage signals or pixel current signals are binned.

Abstract: An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a differential amplifier. In operation, both pixels are reset at the same time, causing differential reset signals to be output from the amplifier. The charge from the first pixel is readout and a differential pixel signal for the first pixel is output from the amplifier. Because the reset and pixel signals are differential signals generated within the pixels, they are free from common-mode noise. Correlated double sampling can be used to obtain the pixel output value, which is also free from common-mode noise, from the differential reset and pixel signals. The second pixel may be readout in the same manner. Because the two pixels are sharing circuitry, the pixels have decreased fill factor and complexity as well.

Abstract: Imaging sensors having dual-port for digital readout to pipeline readout processes of two different groups of pixels.

Abstract: An A/D converter element of the successive approximation type uses its capacitors both for conversion and for calibration. A calibration face is carried out in which calibration values are obtained. These values are stored and then later used for adjustment of the values obtained from the capacitors.