Patents by Inventor Nikolaos Papandreou

Nikolaos Papandreou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Calibration of open blocks in NAND flash memory
    Patent number: 10614881
    Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • REDUCING EFFECTS OF READ ARRAY OPERATIONS OF READ APPARENT VOLTAGE
    Publication number: 20200104071
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 2, 2020
    Inventors: Kevin E. Sallese, Timothy J. Fisher, Adalberto G. Yanes, Jason Szecheong Ma, Charles A. Keller, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
  • ADDRESSING PAGE-CORRELATED READ ISSUES USING INTRA-BLOCK PARITY
    Publication number: 20200081831
    Abstract: A method for intra-block recovery from memory page read failures of memory pages is provided. The method comprises providing a data storage device comprising a plurality of memory pages. Corresponding memory pages are physically organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells. The method comprises grouping memory pages of a block into at least one window. Each window comprises a plurality of memory pages of the block. The method further comprises determining a window parity page for each window of the block for a recovery of page read failures of the memory pages of the block, and upon determining that a predefined number of memory pages of the window is written or not yet written, maintaining the determined window parity page as part of the related window of memory pages of the block or not.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman Alexander Pletka, Nikolas Ioannou
  • ADDRESSING PAGE-CORRELATED READ ISSUES USING INTRA-BLOCK PARITY
    Publication number: 20200081661
    Abstract: A method for intra-block recovery of an Erasure Code protected memory page stripe may be provided. The method comprises providing a data storage device comprising a plurality of EC protected memory page stripes, each of which comprising a plurality of memory pages, wherein corresponding memory pages of the plurality of the page stripes are organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells, and wherein each page stripe comprises at least one stripe parity page, grouping memory pages of a block into at least one window, each window comprising a plurality of memory pages of the block, and maintaining at least one parity page for each window of the block, such that a page read failure is recoverable even if multiple memory pages per page stripe experience a read failure concurrently.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman Alexander Pletka, Nikolas Ioannou
  • CALIBRATION OF OPEN BLOCKS IN NAND FLASH MEMORY
    Publication number: 20200082878
    Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • SELECTIVE PAGE CALIBRATION BASED ON HIERARCHICAL PAGE MAPPING
    Publication number: 20200066355
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy J. Fisher
  • ERROR RECOVERY OF DATA IN NON-VOLATILE MEMORY DURING READ
    Publication number: 20200066354
    Abstract: A method of optimizing a read threshold voltage shift value for non-volatile memory units organized as memory pages may be provided. An ECC check is performed for active page reads. The method comprises, as part of the read operation, determining a status of the memory page, and reading a memory page with a current threshold voltage shift (TVS) value. Additionally, the method comprises, upon determining that a read memory page command passed an ECC check, returning corrected data read, and upon determining that the read memory page did not pass the ECC check, adjusting the current TVS value based on the status of the memory page to be read. Furthermore, the method comprises, while the read memory pages continues to not pass the ECC check, repeating the adjusting the current TVS value and the determining that the read memory page passes ECC check until a stop condition is met.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Nikolas Ioannou, Charalampos Pozidis, Sasa Tomic, Nikolaos Papandreou, Roman A. Pletka, Aaron D. Fry, Timothy Fisher
  • ADAPTIVE READ VOLTAGE THRESHOLD CALIBRATION IN NON-VOLATILE MEMORY
    Publication number: 20200066353
    Abstract: A non-volatile memory includes a plurality of physical pages each assigned to one of a plurality of page groups. A controller of the non-volatile memory performs a first calibration read of a sample physical page of a page group of the non-volatile memory. The controller determines if an error metric observed for the first calibration read of the sample physical page satisfies a calibration threshold. The controller calibrates read voltage thresholds of the page group utilizing a first calibration technique based on a determination that the error metric satisfies the calibration threshold and calibrates read voltage thresholds of the page group utilizing a different second calibration technique based on a determination that the error metric does not satisfy the calibration threshold.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Roman A. Pletka, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Timothy Fisher, Aaron D. Fry
  • METHODS FOR READ THRESHOLD VOLTAGE SHIFTING IN NON-VOLATILE MEMORY
    Publication number: 20200066361
    Abstract: A method for optimizing a read threshold voltage shift value in a NAND flash memory may be provided. The method comprises selecting a group of memory pages, determining a current threshold voltage shift (TVS) value, and determining a negative and a positive threshold voltage shift offset value. Then, the method comprises repeating a loop process comprising reading all memory pages with different read TVS values, determining maximum raw bit error rates for the group of memory pages, determining a direction of change for the current TVS value, determining a new current TVS value by applying a function to the current TVS value using as parameters the current threshold voltage, the direction of change and the positive and the negative TVS value, until a stop condition is fulfilled such that a lowest possible number of read errors per group of memory pages is reached.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Nikolas Ioannou, Charalampos Pozidis, Nikolaos Papandreou, Roman Alexander Pletka, Sasa Tomic, Aaron D. Fry, Timothy Fisher
  • CALIBRATION OF OPEN BLOCKS IN NAND FLASH MEMORY
    Publication number: 20200051621
    Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • Background mitigation reads in a non-volatile memory system
    Patent number: 10552063
    Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • BACKGROUND MITIGATION READS IN A NON-VOLATILE MEMORY SYSTEM
    Publication number: 20190391746
    Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • BLOCK HEALTH ESTIMATION FOR WEAR LEVELING IN NON-VOLATILE MEMORIES
    Publication number: 20190391752
    Abstract: In at least one embodiment, a controller of a non-volatile memory having a plurality of blocks of physical memory estimates a current value of a block health metric of the particular block based on a previous value of the block health metric and a reference block wear curve. The controller assigns the particular block a health grade based on the estimated current value of the block health metric and performs data placement in the block in accordance with the assigned health grade. The controller may calibrate a set of read threshold voltages of the particular block prior to estimating the current value of the block health metric.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Roman A. Pletka, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Aaron D. Fry, Timothy Fisher
  • Reducing read errors by performing mitigation reads to blocks of non-volatile memory
    Patent number: 10489086
    Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Adalberto G. Yanes, Timothy Fisher, Charles A. Keller, Jason S. Ma, Kevin E. Sallese, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
  • MITIGATING ASYMMETRIC TRANSIENT ERRORS IN NON-VOLATILE MEMORY BY PROACTIVE DATA RELOCATION
    Publication number: 20190347013
    Abstract: A controller performs background reads of multiple physical pages of a selected physical block of a non-volatile memory. The controller detects asymmetric transient errors in a physical page among the multiple physical pages based on a bit error rate (BER) observed in the background read of the physical page. In response to detecting the asymmetric transient errors, the controller mitigates the detected asymmetric transient errors by relocating valid logical pages of data from the physical page to another physical block of the non-volatile memory and by retaining valid logical pages of data programmed into other physical pages of the selected physical block.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: ROMAN A. PLETKA, NIKOLAOS PAPANDREOU, SASA TOMIC, NIKOLAS IOANNOU, AARON D. FRY, TIMOTHY FISHER
  • TECHNIQUES FOR REDUCING READ VOLTAGE THRESHOLD CALIBRATION IN NON-VOLATILE MEMORY
    Publication number: 20190348130
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: MATT REUTER, SASA TOMIC, NIKOLAOS PAPANDREOU, TIMOTHY FISHER, AARON D. FRY, ROMAN A. PLETKA, NIKOLAS IOANNOU, CHARALAMPOS POZIDIS
  • REDUCING READ ERRORS BY PERFORMING MITIGATION READS TO BLOCKS OF NON-VOLATILE MEMORY
    Publication number: 20190339902
    Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: ADALBERTO G. YANES, TIMOTHY FISHER, CHARLES A. KELLER, JASON S. MA, KEVIN E. SALLESE, AARON D. FRY, VAN HUYNH, NIKOLAOS PAPANDREOU
  • ACCELERATING GARBAGE COLLECTION OF FLUSHED LOGICAL ERASE BLOCKS IN NON-VOLATILE MEMORY
    Publication number: 20190340121
    Abstract: A controller of a non-volatile memory tracks identifiers of logical erase blocks (LEBs) for which programming has closed. A first subset of the closed LEBs tracks LEBs that are ineligible for selection for garbage collection, and a second subset of the closed LEBs tracks LEBs that are eligible for selection for garbage collection. The controller continuously migrates closed LEBs from the first subset to the second subset over time. In response to closing a particular LEB, the controller places an identifier of the particular LEB into one of the first and second subsets selected based on a first amount of dummy data programmed into the closed LEBs tracked in the first subset. Thereafter, in response to selection of the particular LEB for garbage collection, the controller performs garbage collection on the particular LEB.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: ROMAN A. PLETKA, NIKOLAOS PAPANDREOU, SASA TOMIC, NIKOLAS IOANNOU
  • Accelerating garbage collection of flushed logical erase blocks in non-volatile memory
    Patent number: 10459839
    Abstract: A controller of a non-volatile memory tracks identifiers of logical erase blocks (LEBs) for which programming has closed. A first subset of the closed LEBs tracks LEBs that are ineligible for selection for garbage collection, and a second subset of the closed LEBs tracks LEBs that are eligible for selection for garbage collection. The controller continuously migrates closed LEBs from the first subset to the second subset over time. In response to closing a particular LEB, the controller places an identifier of the particular LEB into one of the first and second subsets selected based on a first amount of dummy data programmed into the closed LEBs tracked in the first subset. Thereafter, in response to selection of the particular LEB for garbage collection, the controller performs garbage collection on the particular LEB.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou
  • Techniques for reducing read voltage threshold calibration in non-volatile memory
    Patent number: 10453537
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matt Reuter, Sasa Tomic, Nikolaos Papandreou, Timothy Fisher, Aaron D. Fry, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis