Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Abstract: Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.

Abstract: An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.

Abstract: A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.

Abstract: According to one embodiment, a method, computer system, and computer program product for training a cognitive model that involves one or more decision trees as base learners is provided. The present invention may include constructing, by a tree building algorithm, the one or more decision trees, wherein the constructing further comprises associating one or more training examples with one or more leaf nodes of the one or more decision trees and iteratively running a breadth-first search tree builder on one or more of the decision trees to perform one or more tree building operations; and training the cognitive model based on the one or more decision trees.

Abstract: A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.

Abstract: A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.

Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.

Abstract: Processing a digital image in a distributed computing environment comprising a communications network interconnecting two or more computing nodes. A segmentation of the digital image into two or more image segments is determined. For each of the image segments, a number of non-background pixels comprised by the image segment is determined. An assignment of each of the image segments to one of the computing nodes is determined. The determination of the assignment may include balancing, based on the number of non-background pixels determined for each of the image segments, the workload of the assigned computing nodes responsive to processing the image segments. Each of the assigned computing nodes may be caused to process the image segments assigned to the computing node.

Abstract: A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.

Abstract: Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

Abstract: The present invention is notably directed to a computer-implemented method of training a cognitive model. The cognitive model includes decision trees as base learners. The method is performed using processing means to which a given cache memory is connected, so as to train the cognitive model based on training examples of a training dataset. The cognitive model is trained by running a hybrid tree building algorithm, so as to construct the decision trees and thereby associate the training examples to leaf nodes of the constructed decision trees, respectively. The hybrid tree building algorithm involves a first routine and a second routine. Each routine is designed to access the cache memory upon execution. The first routine involves a breadth-first search tree builder, while the second routine involves a depth-first search tree builder.

Abstract: A computer-implemented method, according to one embodiment, is for wear leveling blocks of memory. The computer-implemented method includes: determining the health of blocks of memory which are configured in multi-bit-per-cell mode. The blocks configured in multi-bit-per-cell mode are in a second pool, while blocks that are configured in single-level cell (SLC) mode are in a first pool. Moreover, the computer-implemented method is performed in some approaches with a proviso that the health of a block of memory is not determined while the block is configured in SLC mode. Moreover, health values are assigned to the blocks of memory in the second pool based on the health of the respective block. Each of the health values is further correlated with a respective data temperature.

Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.

Abstract: A computer-implemented method, according to one embodiment, is for maintaining heat information of data while in a cache. The computer-implemented method includes: transferring data from non-volatile memory to the cache, such that the data is stored in a first page in the cache. Previous read and/or write heat information associated with the data is maintained by preserving one or more bits in a hash table which correspond to the data in the first page. Moreover, the data is destaged from the first page in the cache to the non-volatile memory, and the one or more bits in the hash table which correspond to the data are updated to reflect current read and/or write heat information associated with the data.

Abstract: A memory system, Reed Solomon (“RS”) Decoder, and method for decoding Reed-Solomon codewords includes: a Syndrome Computation engine configured as a first stage of a pipeline for receiving the RS codeword and computing one or more Syndromes; an initialization unit for providing initialization values for a key equation solver engine that generates the errata locator polynomial and the errata magnitude polynomial configured as a second stage; and as a third stage a Chien Search engine for receiving the error locator polynomial and determining the one or more locations of the one or more erasures and random errors in the received RS codeword and an error-value evaluation (“EE”) engine for receiving the errata magnitude polynomial and determining the one or more magnitudes of the one or more erasures and random errors in the RS received codeword.

Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a RTU queue associated with a first block pool is in a first predetermined range. In response to determining that the number of blocks included in the RTU queue is not in the first predetermined range, a determination is made as to whether a current I/O workload is in a second predetermined range. In response to determining that the current I/O workload is in the second predetermined range, for each block in the first block pool having a desired amount of metadata associated with the pages in the given block: a subset of pages in the given block are selected and data is relocated therefrom to a block in the second block pool.

Abstract: Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.