Abstract: Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Abstract: In an approach for constructing an ensemble model from a set of base learners, a processor performs a plurality of boosting iterations, where: at each boosting iteration of the plurality of boosting iterations, a base learner is selected at random from a set of base learners, according to a sampling probability distribution of the set of base learners, and trained according to a training dataset; and the sampling probability distribution is altered: (i) after selecting a first base learner at a first boosting iteration of the plurality of boosting iterations and (ii) prior to selecting a second base learner at a final boosting iteration of the plurality of boosting iterations. A processor constructs an ensemble model based on base learners selected and trained during the plurality of boosting iterations.

Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Abstract: A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Abstract: Live migration of a virtual machine (VM) includes establishing multipath connections between the VM and functions of host interface on a source host. The multipath connections include a passthrough path and a software-virtualized (or emulated) path provided by a hypervisor of the source host. A failover of the passthrough path to the emulated path is executed, and a state of the emulated path is thereafter saved. On a host interface of a destination host, functions corresponding to those of the source host are exposed. The VM is then migrated from the source host to the destination host. The VM resumes host interface communication with the host interface of the destination host from the saved state via an emulated path provided by a hypervisor of the destination host. After resuming communication, a passthrough path of communication between the VM and the host interface of the destination host is established.

Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.

Abstract: Parallel training of a machine learning model on a computerized system is described. Computing tasks of a system can be assigned to multiple workers of the system. Training data can be accessed. The machine learning model is trained, whereby the training data accessed are dynamically partitioned across the workers of the system by shuffling subsets of the training data through the workers. As a result, different subsets of the training data are used by the workers over time as training proceeds. Related computerized systems and computer program products are also provided.

Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.

Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.

Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Abstract: A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Abstract: An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.