Patents by Inventor Nikolas Ioannou

Nikolas Ioannou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210124488
    Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Radu Ioan Stoica, Roman Alexander Pletka, Timothy Fisher, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou, Aaron Daniel Fry, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210117118
    Abstract: A computer-implemented method, according to one embodiment, is for managing a plurality of blocks of memory in two or more pools. The computer-implemented method includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in single-level cell (SLC) mode. A second subset of the plurality of blocks is also maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. Current workload input/output (I/O) metrics are also identified during runtime. Moreover, a size of the first subset of blocks in the first pool and a size of the second subset of blocks in the second pool are adjusted based on the current workload I/O metrics.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventors: Radu Ioan Stoica, Roman Alexander Pletka, Nikolas Ioannou, Nikolaos Papandreou, Sasa Tomic
  • Publication number: 20210109811
    Abstract: A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roman Alexander PLETKA, Sasa TOMIC, Timothy FISHER, Nikolaos PAPANDREOU, Nikolas IOANNOU, Aaron FRY
  • Publication number: 20210109807
    Abstract: A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Sasa Tomic
  • Patent number: 10977181
    Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Patent number: 10963327
    Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Roman Pletka, Sasa Tomic
  • Patent number: 10957407
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Patent number: 10956049
    Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Roman Alexander Pletka, Nikolas Ioannou, Nikolaos Papandreou, Aaron D. Fry, Timothy Fisher, Radu Ioan Stoica
  • Patent number: 10956317
    Abstract: A non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block. The controller ends garbage collection on the at least one source block with at least some valid data present in the at least one source block and all interfaces of the target block closed at the boundary of independent layers. In at least some embodiments, the target block may be configured to store more bits per cell than the at least one source block.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou, Aaron D. Fry, Timothy Fisher
  • Patent number: 10942808
    Abstract: Embodiments for adaptive placement of parity information within Redundant Array of Independent Disks (RAID) stripes in a computer storage environment. A RAID controller periodically collects a physical capacity usage of each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the physical capacity usage. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roman Alexander Pletka, Sasa Tomic, Timothy Fisher, Nikolaos Papandreou, Nikolas Ioannou, Aaron Fry
  • Patent number: 10942662
    Abstract: A computer-implemented method, according to one embodiment, includes: calibrating a first block of storage space in memory, identifying a page in the calibrated first block having a highest RBER, and determining whether the RBER of the identified page is greater than an error correction code limit. In response to determining that the RBER of the identified page is not greater than the error correction code limit, a determination is made as to whether the RBER of the identified page is greater than a relocation limit. In response to determining that the RBER of the identified page is not greater than a relocation limit, another determination is made as to whether the first block has been excessively calibrated. Furthermore, in response to determining that the first block has been excessively calibrated, data in the first block relocated to a second block of storage space in the memory.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Aaron D. Fry, Timothy J. Fisher
  • Publication number: 20210065813
    Abstract: A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry, Andrew D. Walls
  • Patent number: 10929069
    Abstract: A method for intra-block recovery of an Erasure Code protected memory page stripe may be provided. The method comprises providing a data storage device comprising a plurality of EC protected memory page stripes, each of which comprising a plurality of memory pages, wherein corresponding memory pages of the plurality of the page stripes are organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells, and wherein each page stripe comprises at least one stripe parity page, grouping memory pages of a block into at least one window, each window comprising a plurality of memory pages of the block, and maintaining at least one parity page for each window of the block, such that a page read failure is recoverable even if multiple memory pages per page stripe experience a read failure concurrently.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Nikolaos Papandreou, Roman Alexander Pletka, Nikolas Ioannou
  • Patent number: 10929229
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request at a storage system which includes more than one storage device, determining a storage location for data included in the write request, and determining a storage location for parity information corresponding to the data included in the write request. A first copy of the data included in the write request is sent to a first storage device which corresponds to the storage location for the data included in the write request. Moreover, a second copy of the data included in the write request is sent to a second storage device which corresponds to the storage location for the parity information. One or more instructions to compute the parity information via a decentralized communication link with the remaining storage devices are sent to the second storage device. The first storage device is different than the second storage device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Radu I. Stoica, Roman A. Pletka, Ioannis Koltsidas, Nikolas Ioannou, Antonios K. Kourtis, Sasa Tomic, Charalampos Pozidis, Brent W. Yardley
  • Publication number: 20210042239
    Abstract: A computer-implemented method, according to one embodiment, is for maintaining heat information of data while in a cache. The computer-implemented method includes: transferring data from non-volatile memory to the cache, such that the data is stored in a first page in the cache. Previous read and/or write heat information associated with the data is maintained by preserving one or more bits in a hash table which correspond to the data in the first page. Moreover, the data is destaged from the first page in the cache to the non-volatile memory, and the one or more bits in the hash table which correspond to the data are updated to reflect current read and/or write heat information associated with the data.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Nikolas Ioannou, Nikolaos Papandreou, Roman Alexander Pletka, Sasa Tomic, Radu Ioan Stoica, Timothy Fisher, Aaron Daniel Fry, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210011852
    Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210004158
    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Aaron Daniel Fry, Timothy Fisher, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210004159
    Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a block switching metric for each block of memory in the storage system. A determination is made as to whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block. In response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, the first block is erased. The first block is then transferred from the first pool to a second RTU queue which corresponds to the second pool. A second block in the second pool is also erased and transferred from the second pool to a first RTU queue which corresponds to the first pool.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Patent number: 10884914
    Abstract: A technique for garbage collection in a storage system includes generating regrouping metadata for one or more pages of at least two logical erase blocks (LEB). The regrouping metadata indicates an associated stream for each of the pages. Multiple of the LEBs that include valid pages associated with a first stream are selected, based on the regrouping metadata, for regrouping. The valid pages associated with the first stream from the selected LEBs are regrouped into a new LEB.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Razik S. Ahmed, Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Jason Ma, Matthew R. Orr, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Publication number: 20200393972
    Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 17, 2020
    Inventors: Sasa Tomic, Roman Alexander Pletka, Nikolas Ioannou, Nikolaos Papandreou, Aaron D. Fry, Timothy Fisher, Radu Ioan Stoica