Patents by Inventor Nikos Kaburlasos

Nikos Kaburlasos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117060
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 12, 2024
    Publication date: April 10, 2025
    Applicant: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Publication number: 20250117875
    Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 9, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Nikos Kaburlasos, Josh B. Mastronarde
  • Publication number: 20250103343
    Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 27, 2025
    Applicant: INTEL CORPORATION
    Inventors: Christopher J. HUGHES, Prasoonkumar SURTI, Guei-Yuan LUEH, Adam T. LAKE, Jill BOYCE, Subramaniam MAIYURAN, Lidong XU, James M. HOLLAND, Vasanth RANGANATHAN, Nikos KABURLASOS, Altug KOKER, Abhishek R. Appu
  • Publication number: 20250103430
    Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
    Type: Application
    Filed: October 4, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Nikos Kaburlasos, Lidong Xu, Subramaniam Maiyuran, Altug Koker, Naveen Matam, James Holland, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Durgaprasad Bilagi, Xinmin Tian
  • Patent number: 12253901
    Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Rodrigo De Oliveira Vivi, Phani Kumar Kandula, Marc Beuchat, Mark J. Luckeroth, Eric J. M. Moret, David N. Lombard, John Kelbert, Brad Bittel
  • Publication number: 20250080941
    Abstract: An apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. The processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. The processor circuitry is to adjust, based on the movement of the head of the user, the first audio data for the first channel and the second audio data for the second channel. The processor circuitry is to cause the adjusted first audio data and the adjusted second audio data to be played by the earphones.
    Type: Application
    Filed: September 25, 2024
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell
  • Patent number: 12229871
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer K P, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Patent number: 12205192
    Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: January 21, 2025
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Nikos Kaburlasos, Josh B. Mastronarde
  • Patent number: 12190118
    Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: January 7, 2025
    Assignee: INTEL CORPORATION
    Inventors: Christopher J. Hughes, Prasoonkumar Surti, Guei-Yuan Lueh, Adam T. Lake, Jill Boyce, Subramaniam Maiyuran, Lidong Xu, James M. Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Abhishek R. Appu
  • Publication number: 20240404487
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 5, 2024
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
  • Patent number: 12147302
    Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Nikos Kaburlasos, Lidong Xu, Subramaniam Maiyuran, Altug Koker, Naveen Matam, James Holland, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Durgaprasad Bilagi, Xinmin Tian
  • Publication number: 20240354043
    Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
    Type: Application
    Filed: April 29, 2024
    Publication date: October 24, 2024
    Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
  • Patent number: 12126988
    Abstract: An apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. The processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. The processor circuitry is to adjust, based on the movement of the head of the user, the first audio data for the first channel and the second audio data for the second channel. The processor circuitry is to cause the adjusted first audio data and the adjusted second audio data to be played by the earphones.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell
  • Patent number: 12124310
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: October 22, 2024
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Patent number: 12108239
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Publication number: 20240310889
    Abstract: An apparatus for managing a power consumption of processor or memory circuitry comprising a plurality of processing or memory functional units may be provided. The processor or memory circuitry is arranged to receive electrical power from an alternating current, AC, power source or a battery. The apparatus comprises processing circuitry to: based on an indication that the processor or memory circuitry is receiving electrical power from the AC power source, selectively cause operational electrical power to be provided to a first number of the functional units of the processor or memory circuitry. The processing circuitry is further to: based on an indication that the circuitry is receiving electrical power from the battery, selectively cause operational electrical power to be provided to a second number of the functional units of the processor or memory circuitry, the second number being less than the first number.
    Type: Application
    Filed: September 22, 2021
    Publication date: September 19, 2024
    Inventor: Nikos KABURLASOS
  • Publication number: 20240288927
    Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 12, 2024
    Publication date: August 29, 2024
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Josh B. Mastronarde, Nikos Kaburlasos
  • Patent number: 12061831
    Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
  • Patent number: 12014701
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
  • Patent number: 11989076
    Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 21, 2024
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Josh B. Mastronarde, Nikos Kaburlasos