Abstract: Tightly-coupled, loosely connected distributed systems can be implemented more energy efficient and optimized for computational overhead via multi-protocol heterogeneous packet-based transport. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets can be handled via Direct Memory Access. A write-only communication scheme can be implemented using doorbell and command registers for more efficient data reading and writing in distributed systems.

Abstract: Deterministic real-time multi-protocol heterogeneous packet-based transport is achieved by traffic shaping. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets pass traffic scheduling or traffic shaping prior being sent via a plurality of connections to avoid burstiness and to achieve bounded transport latency in the plurality of connections, thereby providing deterministic real-time behavior in distributed systems.

Abstract: Deterministic real-time multi-protocol heterogeneous packet-based transport is achieved by traffic shaping. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets pass traffic scheduling or traffic shaping prior being sent via a plurality of connections to avoid burstiness and to achieve bounded transport latency in the plurality of connections, thereby providing deterministic real-time behavior in distributed systems.

Abstract: Deadlocks in a multi-protocol heterogeneous packet-based transport system are avoided while maintaining real-time aspects. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Deadlocks in a multi-protocol heterogeneous packet-based transport system are avoided while maintaining real-time aspects. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: For secure transport, when receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encrypted and encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: For secure transport, when receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encrypted and encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

Abstract: Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Within a partitioned system, a first system partition operates in a safety domain in which predictable operation of the first system partition is necessary to protect the system or operators of the system from harm. A second system partition operates in a user domain in which information supplied by the second system partition is not sufficiently reliable to be used by the first system partition within the safety domain. A mediator controller is connected between the first system partition and the second system partition. The mediator controller receives the information supplied by the first system partition. The mediator controller monitors and supervises use of the information by the second system partition in order maintain requirements of the safety domain to protect the system or operators of the system from harm.

Abstract: An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

Abstract: Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

Abstract: An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

Abstract: Within a partitioned system, a first system partition operates in a safety domain in which predictable operation of the first system partition is necessary to protect the system or operators of the system from harm. A second system partition operates in a user domain in which information supplied by the second system partition is not sufficiently reliable to be used by the first system partition within the safety domain. A mediator controller is connected between the first system partition and the second system partition. The mediator controller receives the information supplied by the first system partition. The mediator controller monitors and supervises use of the information by the second system partition in order maintain requirements of the safety domain to protect the system or operators of the system from harm.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. A HDL design instrumentation circuitry embedded within an electronic system comprises one or more probe circuits to allow storage of signal values of the electronic system upon predetermined events, one or more breakpoint registers to specify the predetermined events, and one or more trigger processing units to control the storage of signal values upon the detection of the predetermined events by the breaking registers. The present design instrumentation circuitry permits monitoring the electronic system at speed, facilitating the analysis diagnosis and debugging by giving detailed and accurate information about the operation of the electronic system.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.