Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state.

Abstract: Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.

Abstract: Various embodiments of the present invention provide systems and methods for determining fly height. For example, a system for fly height determination is disclosed that includes a head assembly disposed in relation to a storage medium, a write channel, and a read circuit. The read circuit is operable to receive information from both the head assembly and the write channel. A frequency determination circuit is included that is operable to receive a first signal from the read circuit corresponding to information received from the write channel and to provide a first fundamental frequency and a first higher order frequency based on the first signal, and the frequency determination circuit is operable to receive a second signal from the read circuit corresponding to information received from the head assembly channel and to provide a second fundamental frequency and a second higher order frequency based on the second signal.

Abstract: A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. At least one register and at least one pointer are maintained for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. A trellis transition type is determined, for example, based on a decision from an add/compare/select unit. One or more predefined rules based on a trellis structure and the trellis transition type are employed to exchange one or more of the pointers and to update one or more of the at least one registers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a latch for storing one bit of a bit sequence associated with a Viterbi state.

Abstract: Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.

Abstract: In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log2 m) MLCs are used to store the p-symbol codeword (iii) each MLC stores one symbol of the codeword. The energy-saving decoder is adapted to read p-symbol codewords from the MLC NAND flash memory and decode each p-symbol codeword into a k-bit segment of raw user data for provision to the host controller. The host controller is adapted to vary k and n to conserve usage of power or memory-space, as needed.

Abstract: A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital hack end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.

Abstract: A method for generating soft bit values for a multi-bit symbol encoded in one or more received signals comprises (a) for a plurality of different combinations of multiple bit values, iteratively generating, for each combination, a metric value based on the one or more received signals. The method further comprises (b) for each iteration, maintaining (i) a global extremum register containing a global extremum of the metric values; (ii) a bit occupancy for the global extremum register; and (iii) a plurality of bit bk registers, one for each bit bk in the symbol. Each bit bk register contains an extremum of the metric values corresponding to combinations of multiple bit values whose bit bk value is opposite the bit bk value of the bit occupancy for the global extremum register. The method further comprises (c) generating, for each bit bk in the symbol, a soft bit value based on a difference between the value in the global extremum register and the value in the corresponding bit bk register.

Abstract: In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.

Abstract: Various embodiments of the present invention provide systems and methods for determining fly height. For example, a system for fly height determination is disclosed that includes a head assembly disposed in relation to a storage medium, a write channel, and a read circuit. The read circuit is operable to receive information from both the head assembly and the write channel. A frequency determination circuit is included that is operable to receive a first signal from the read circuit corresponding to information received from the write channel and to provide a first fundamental frequency and a first higher order frequency based on the first signal, and the frequency determination circuit is operable to receive a second signal from the read circuit corresponding to information received from the head assembly channel and to provide a second fundamental frequency and a second higher order frequency based on the second signal.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: An improved mass storage system having a read channel adapted to store in a FIFO memory digitized analog samples of data symbols read from a disk, the buffered digitized samples being processed by digital circuitry that may be operated at a slower speed than the maximum symbol rate from the disk. In one embodiment, the read channel has an analog portion that processes analog signals from a read head and includes an ADC for converting the processed analog signals into digital samples in response to a first clock; a FIFO storing therein the digital samples in response to the first clock and reading out the stored digital samples in response to a second clock; and a detector, in response to the second clock, detecting the digital samples from the FIFO into digital data. The maximum frequency of the first clock is less than the maximum frequency of the second clock.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.