Abstract: In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and wc check node messages, where wc is the column hamming weight of the LDPC code. The VNU generates (i) an extrinsic log-likelihood ratio (LLR) by adding all wc check node messages together; (ii) a hard-decision output by adding the extrinsic LLR to the soft-input value and selecting the sign bit of the resulting sum; and (iii) wc variable node messages. Each variable node message is generated by adding a different set of (wc?1) check node messages to the soft-input value where each set excludes a different check node message. In so doing, VNUs of the present invention may generate variable node messages using fewer adder stages compared to prior-art VNUs such that throughput may be increased over that of prior-art VNUs.

Abstract: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.

Abstract: Various systems and methods for low power multi-rate data paths are disclosed. As one example, a semiconductor device that includes a multi-rate data path is discussed. The multi-rate data path includes at least two register circuits with an output of one of the register circuits electrically coupled to an input of the other register circuit via a combinational logic block. In addition, the semiconductor device includes a control circuit that is operable to modify the rate at which the multi-rate data path operates by selectably bypassing at least one of the register circuits.

Abstract: Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

Abstract: Various systems and methods for music recognition are disclosed herein. For example, music recognition devices are disclosed that include a data receiver that is operable to receive a data signal incorporating an identification of a currently playing song. The devices further include a memory and a processor. The memory includes instructions executable by the processor to: parse the data signal and to cause the identification to be stored to the memory. At least a portion of the identification is maintained in the memory after the currently playing song has terminated.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set.

Abstract: A method for detecting a symbol encoded in one or more received signals, wherein the detected symbol corresponds to a combination of values of n components, n>1, comprises (a) for each of a plurality of different combinations of values of the n components, generating a set of two or more sub-metric values based on the one or more received signals. Each sub-metric is a function of one or more of the n components, and at least one sub-metric is a function of fewer than all n components. The method further comprise (b) detecting the symbol based on the sets of sub-metric values. In another embodiment, an apparatus for detecting a symbol encoded in one or more received signals, wherein the detected symbol corresponds to a combination of values of n components, n>1, comprises (a) means for generating a set of two or more sub-metric values based on the one or more received signals for each of a plurality of different combinations of values of the n components.

Abstract: In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log2m) MLCs are used to store the p-symbol codeword (iii) each MLC stores one symbol of the codeword. The energy-saving decoder is adapted to read p-symbol codewords from the MLC NAND flash memory and decode each p-symbol codeword into a k-bit segment of raw user data for provision to the host controller. The host controller is adapted to vary k and n to conserve usage of power or memory-space, as needed.

Abstract: Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a status memory is maintained for each of the N states of the trellis, wherein each entry in the status memory identifies a least recent trellis state stored in the trellis memory of a survivor path that begins at a given state on a side of the trellis associated with most recent states. A bit sequence of one or more of the survivor paths in the trellis is determined in an order that the bits are received by examining least and most recent trellis stages of the trellis and the status memory. One or fork memories maintain an indicator of whether a given fork is active; a list of active forks; a trellis position of active forks in the trellis; and a fork type of one or more forks in the trellis.

Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.

Abstract: Various systems and methods for power reduction are disclosed herein. As one example, a method for power reduction in a semiconductor device is disclosed. The method includes providing a semiconductor device that includes a bus. The bus includes a group of signals and a control signal associated with the group of signals. In one particular case, the group of signals is a data bus and the control signal is a low frequency signal implementing some particular control specific to the bus. In the method, the control signal doubles as a polarity control that indicates a polarity state of the group of signals while actively indicating the status of the particular control.

Abstract: A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

Abstract: A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.

Abstract: An improved mass storage system having a read channel adapted to store in a FIFO memory digitized analog samples of data symbols read from a disk, the buffered digitized samples being processed by digital circuitry that may be operated at a slower speed than the maximum symbol rate from the disk. In one embodiment, the read channel has an analog portion that processes analog signals from a read head and includes an ADC for converting the processed analog signals into digital samples in response to a first clock; a FIFO storing therein the digital samples in response to the first clock and reading out the stored digital samples in response to a second clock; and a detector, in response to the second clock, detecting the digital samples from the FIFO into digital data. The maximum frequency of the first clock is less than the maximum frequency of the second clock.

Abstract: Various embodiments of the present invention provide systems and methods for responding to business related queries. As one example, such methods may include providing a communication direction associated with a particular business, and receiving a query via the communication direction. The received query is directed to a third party support service where it is parsed and one or more elements of the query are compared against a prior query. A response to the query was previously supplied by the particular business. A response is provided to the query that includes at least a portion of the reply to the prior query.

Abstract: Various embodiments of the present invention provide systems and methods for LDPC encoding and decoding. For example, a system for performing LDPC encoding and decoding is disclosed that includes a joint LDPC encoder/decoder. The joint LDPC encoder/decoder includes both an LDPC decoder and an LDPC encoder that each utilize a common LDPC decoder circuit to perform the respective functions of encoding and decoding.

Abstract: Various systems and methods for indicating the status of a communication are disclosed herein. For example, status indication methods are disclosed that include initiating a communication that allows for communication between two persons. Further, the methods include determining a combination of status. The combination of status is based on a determination of two or more of the following: a calendar status, a power status, an activity status, and a location status. A communication status message is updated based at least in part on the determined combination of status.

Abstract: System and Methods for Copying Digital Information from a Digital Media Various embodiments of the present invention provide systems and methods for copying or ripping digital information contained on one media to another media. In particular, some embodiments of the present invention provide methods and systems for copying digital information contained in a first fixed media onto another media by using digital information content corresponding to that maintained on the first fixed media, but obtained from a database.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.