Patents by Inventor Ning Chang

Ning Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190019567
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 17, 2019
    Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
  • Patent number: 10175730
    Abstract: A hinge module including a fixing member, a moving assembly, and a torque member is provided. The moving assembly includes a bracket and an axis body protruding from the bracket. The torque member includes a first end portion and a second end portion opposite to each other. The first end portion is fixed to the fixing member. The second end portion includes a lunular shape axle sleeve with an opening. The lunular shape axle sleeve is rotatably sleeved around the axis body for providing friction so as to form torques while the axis body is rotated relative to the lunular shape axle sleeve. The lunular shape axle sleeve has a gradual changed thickness. An electronic device having the hinge module is further provided.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: January 8, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Ming-Chung Liu, Tung-Ying Wu, Yu-Ning Chang, Che-Hsien Chu
  • Patent number: 10163522
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
  • Publication number: 20180164856
    Abstract: A hinge module including a fixing member, a moving assembly, and a torque member is provided. The moving assembly includes a bracket and an axis body protruding from the bracket. The torque member includes a first end portion and a second end portion opposite to each other. The first end portion is fixed to the fixing member. The second end portion includes a lunular shape axle sleeve with an opening. The lunular shape axle sleeve is rotatably sleeved around the axis body for providing friction so as to form torques while the axis body is rotated relative to the lunular shape axle sleeve. The lunular shape axle sleeve has a gradual changed thickness. An electronic device having the hinge module is further provided.
    Type: Application
    Filed: July 18, 2017
    Publication date: June 14, 2018
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Ming-Chung Liu, Tung-Ying Wu, Yu-Ning Chang, Che-Hsien Chu
  • Patent number: 9993662
    Abstract: A method and apparatus for treatment planning are described.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 12, 2018
    Assignee: ACCURAY INCORPORATED
    Inventors: Hongwu Wang, John R. Dooley, Bai Wang, Jay B. West, I-Ning Chang, Neda Sayan
  • Patent number: 9983257
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Ku-Ning Chang, Yu-Chen Wang
  • Publication number: 20170224814
    Abstract: Disclosed are methods for treating one or more mammalian cancers, and in particular, methods for treating human melanoma, or a head or neck cancer, that employ therapeutically-effective amounts of one or more iNOS pathway-inhibitory compounds, either alone, or in combination with one or more selected antihypertensive agents (including, for example, calcium channel antagonists), alone, or further in combination with one or more conventional chemotherapeutic agents. Also disclosed are pharmaceutical formulations that comprise these compositions, as well as methods for their use in treating refractory, metastatic, and/or relapsed cancers, or, for use in the management or reversal of treatment resistance in one or more such mammalian cancers.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 10, 2017
    Inventor: Jenny Chee Ning Chang
  • Publication number: 20170222943
    Abstract: Aspects of the disclosure provide a method for reordering. The method includes receiving, by a terminal device, a stream of data units from a wireless network. The data units have respective sequence numbers. Further, the method includes reordering at a protocol layer in a protocol stack, the data units for a next process according to the sequence numbers, determining a dependency relationship of a data unit to one or more missing data units that have sequence numbers prior to the data unit, and advancing, out of order of the sequence numbers, the data unit to the next process when the data unit is independent of the one or more missing data units.
    Type: Application
    Filed: January 24, 2017
    Publication date: August 3, 2017
    Applicant: MEDIATEK INC.
    Inventors: YU-TING YAO, Chih-Heng Shih, Yu-Cheng Chen, Shen-Po Lin, Kuo-Chiang Liao, Chia-Ning Chang
  • Publication number: 20170110202
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Wei Cheng Wu, Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Ku-Ning Chang, Yu-Chen Wang
  • Publication number: 20170110201
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
  • Publication number: 20170020835
    Abstract: Disclosed are methods for treating one or more mammalian cancers, and in particular, methods for treating human breast cancer employing one or more iNOS pathway-inhibitory compounds, either alone, or in combination with one or more selected antihypertensive agents, including calcium channel antagonists, either alone, and further in combination with one or more conventional chemotherapeutic or anti-cancer regimens. Also disclosed are particular therapeutic formulations including these compositions, and methods for their use in treating refractory, metastatic, and relapsed cancers, and for managing or reversing treatment resistance in human triple-negative breast cancers in particular.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventor: Jenny Chee Ning Chang
  • Patent number: 9546367
    Abstract: Disclosed are methods and compositions for siRNA-mediated therapy of mammalian diseases. In particular, compositions and methods are disclosed for treatment of therapy-resistant human breast cancers. In exemplary embodiments, siRNA molecules are presented that effectively knock down gene expression of one or more polynucleotides in breast cancer tumor initiating cells.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: January 17, 2017
    Inventors: Jenny Chee Ning Chang, Bhuvanesh Dave
  • Publication number: 20160349909
    Abstract: A portable electronic device includes a first body and a second body. The second body includes a processing unit, and a first touch panel, a second touch panel, a keyboard and at least one detecting module electrically connected to the processing unit, respectively. The keyboard is slidably disposed above the second touch panel, and the detecting module is adapted to detect a position of the keyboard. When the keyboard is located at a first position, the keyboard module covers the second touch panel, and the detecting module transmits a first signal to the processing unit so that the first touch panel is turned on. When the keyboard is located at a second position, the keyboard exposes the second touch panel, and the detecting module transmits a second signal to the processing unit so that the first touch panel is turned off. A touch panel controlling method of the portable electronic device is further provided.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 1, 2016
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Shun Lu, Ming-Chung Liu, Hsin-Chieh Fang, Yu-Wen Cheng, Yu-Ning Chang
  • Patent number: D783598
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 11, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yun Bai, Yu-Wen Cheng, Yu-Ning Chang, Ming-Chung Liu, Ming-Shun Lu
  • Patent number: D783599
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 11, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yun Bai, Yu-Wen Cheng, Yu-Ning Chang, Ming-Chung Liu, Ming-Shun Lu
  • Patent number: D786858
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 16, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Wen Cheng, Ming-Chung Liu, Yu-Ning Chang
  • Patent number: D787501
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 23, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Wen Cheng, Ming-Chung Liu, Yu-Ning Chang
  • Patent number: D787503
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 23, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yun Bai, Ming-Chung Liu, Wang-Hung Yeh, Yu-Wen Cheng, Yu-Ning Chang, Hsin-Chieh Fang
  • Patent number: D810750
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: February 20, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Ning Chang, Hong-Tien Wang, Ming-Chung Liu, Hsin-Chieh Fang, Shih-Chin Chou, Yun Bai
  • Patent number: D812617
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 13, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yun Bai, Wang-Hung Yeh, Ming-Chung Liu, Yu-Wen Cheng, Hsin-Chieh Fang, Yu-Ning Chang