Abstract: Provided are a method and apparatus for calibrating an installation error in a pitch angle of a traffic radar, and a storage medium. The method includes changing the frequency of a traffic radar according to a preset strategy within a preset frequency range; acquiring energy values of echo signals of a preset target at different frequencies in sequence; and in response to determining that the acquired energy values of the echo signals satisfy a preset condition, determining the frequency corresponding to the maximum echo signal energy value as the operating frequency of the traffic radar to calibrate the installation error in the pitch angle of the traffic radar. The preset target is disposed on the ground.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: Disclosed is a high-intensity magnetic tool extension rod. The high-intensity magnetic tool extension rod comprises an extension rod, magnets and magnetic conduction structures. The magnets are symmetrically distributed on a lateral part of the extension rod with an axis center of the extension rod as a center. The magnetic conduction structures are arranged on an axial side of the magnet. The magnetic conduction structures comprise a front magnetic conduction structure and a rear magnetic conduction structure which are respectively arranged on both sides of the magnet. The front magnetic conduction structure is arranged at an adapted tool head connecting end of the extension rod, and the rear magnetic conduction structure is arranged at a receiving tool-driven connecting end of the extension rod.

Abstract: Systems, devices, and methods for managing vertical structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes two adjacent memory cells and a conductive structure between the two adjacent memory cells. Each of the two adjacent memory cells includes a transistor having a semiconductor body, a first terminal, a second terminal, and a gate terminal. The conductive structure is in contact with at least one of semiconductor bodies of the transistors of the two adjacent memory cells, and the conductive structure is spaced from the first terminal and the second terminal of each of the transistors of the two adjacent memory cells.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a second semiconductor structure. The second semiconductor structure includes an array of memory cells, each of the memory cells including a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: The present disclosure relates to memory devices and memory systems. An example memory device includes an array of memory cells and a peripheral circuit. Each of the array of memory cells comprises a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The peripheral circuit is adjacent to the array of memory cells in a second direction perpendicular to the first direction. The peripheral circuit includes a second vertical transistor coupled to one of the array of memory cells through the first vertical transistor of the one of the array of memory cells.

Abstract: A method for sentiment analysis includes that: a feature sequence corresponding to text is obtained, the feature sequence includes encoded features; each encoded feature in the feature sequence is processed by using an attention mechanism, to obtain an attention feature of the text; the attention feature is transferred to a spatial transform feature of the text; an entity attribute of the spatial transform feature is recognized, and sentiment mapping is performed based on the spatial transform feature to obtain a sentiment polarity of the entity attribute.

Abstract: The present application relates to the field of image processing technology, specifically to a lip movement detection method and apparatus, a computer-readable storage medium and an electronic device, solving the problem of weak generalization ability and poor robustness of traditional lip movement detection method. The lip movement detection method provided in an embodiment of the present application determines a lip movement detection result of a user based on a reference interlabial distance of the user in a first image frame, where the reference interlabial distance is determined based on a correspondence between an interlabial distance and a reference value for interlabial distance, thus the reference interlabial distance is a relative value. That is, the reference interlabial distance is not easily affected by factors such as shooting angle and shooting distance, thereby improving the robustness of the lip movement detection method.

Abstract: A stacking structure including a first die and a second die bonded with the first die is provided. The first die has a first region and a second region encircled by the first region. The first die includes first metallization structures having a first seal ring structure and a first bonding structure having first dummy pads located over the first seal ring structure. The second die includes second metallization structures having a second seal ring structure and a second bonding structure having second dummy pads located over the second seal ring structure. The first die and the second die are bonded through bonding of the first and second bonding structures. The first and second seal ring structures are substantially vertically aligned, and the first dummy pads are respectively bonded with the second dummy pads.

Abstract: A speech recognition method. The method includes: performing speech activity detection on speech data to obtain multiple speech segments; determining, for each of the speech segments, a number of speakers involved in the each of the speech segments; for each of at least one of the speech segments with the determined number greater than 1: performing speech separation on the each of at least one of the speech segments to obtain multiple audio segments; performing speech recognition on each of the audio segments to obtain respective first speech recognition results for the audio segments; performing feature extraction on each of the audio segments to obtain respective voiceprint feature vectors; and performing clustering on the audio segments with respect to the speakers to obtain a clustering result; and obtaining a second speech recognition result for the speech data based on the clustering result and the respective first speech recognition results.

Abstract: The present application provides a data processing method, a category identification method and a computer device, in which, firstly, node information is screened out based on node edge data and feature information, that is, K first nodes with rich structures and high feature discrimination are located, and then a feature similarity is calculated based on relevant information of the first nodes. On the other hand, since a calculation amount of the feature similarity of the node is relatively small, for a case that model training and prediction of node category are completed at the same time, a second node can include a node to be classified, and a model parameter used in category prediction is obtained by performing parameter iterative updating with taking the node to be classified as an unlabeled node.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a semiconductor structure including an array of memory cells and a plurality of bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the plurality of bit lines extends in a second direction perpendicular to the first direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are disclosed. The semiconductor device includes an array of vertical transistors. Each vertical transistor includes a semiconductor body extending in a vertical direction, and an all-around gate structure laterally surrounding the semiconductor body. Each row of the vertical transistors in a first lateral direction share a common word line extending in the first lateral direction and comprising the all-around gate structures of the row of the vertical transistors. Adjacent rows of the vertical transistors are misaligned along a second lateral direction perpendicular with the first lateral direction. The array of vertical transistors are aligned along a third lateral direction different from the first lateral direction and the second lateral direction.

Abstract: Embodiments of the present application provide a data processing method and apparatus, an electronic device, and a storage medium. The data processing method, applied to a first participating node, includes: encrypting plaintext service data based on an encryption key array to obtain a ciphertext data set, where the ciphertext data set includes ciphertext service data, and different participating member nodes use a same encryption key array; sending the ciphertext data set to a central node; and acquiring a data comparison result generated by the central node, where the data comparison result is obtained by performing data comparison based on ciphertext service data in ciphertext data sets of the participating member nodes.

Abstract: Antibodies that binds Nectin Cell Adhesion Molecule 4 (nectin-4) and multi-specific protein complexes comprising such anti-nectin4 antibodies, at least one additional antibody moiety binding to another target, and/or at least one cytokine moiety. Also provided herein are pharmaceutical compositions comprising such and uses thereof.

Abstract: The present disclosure provides a kit for detecting an African swine fever virus (ASFV), and provides a corresponding single guide RNA (sgRNA) with a nucleic acid sequence shown in any one of SEQ ID NO: 1 to SEQ ID NO: 5. The kit is based on loop-mediated isothermal amplification (LAMP)-clustered regularly interspaced short palindromic repeat (CRISPR)/Cas12b and can detect the ASFV in one tube at a constant temperature. The kit only needs to set one reaction temperature, does not open its lid midway, and has high sensitivity and specificity while showing no specificity to other swine viruses. The kit exhibits high efficiency and convenience, and does not rely on a large-scale experimental equipment. Compared with the traditional fluorescence quantitative PCR methods, the kit has a greatly improved sensitivity in detecting 1 copy/?L. The kit realizes visual detection by combining with colloidal gold test strip detection.

Abstract: Disclosed herein are high affinity anti-Siglec 15 antibodies and methods of using such for therapeutic and/or diagnostic purposes. Also provided herein are methods for producing such anti-Siglec 15 antibodies.

Abstract: Embodiments of this application provide a method for annotating video data performed by a computer device. The method includes: displaying target video data in a video application; displaying annotated media data in the video application in response to a trigger operation performed on a progress time point annotation function in the video application, the annotated media data being media data associated with a current progress time point, the current progress time point being a progress time point corresponding to the trigger operation to which the target video data is played; and sharing the annotated media data with another user in response to a confirmation operation performed on the annotated media data, the annotated media data enabling the second user to perform a progress jump on the target video data based on the current progress time point. Through this application, efficiency of video progress positioning can be improved.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.