Abstract: A method for compensating pixel luminance of a display panel which includes receiving pixel parameters corresponding to sub-pixels of the display panel, receiving an input image, adjusting the input image according to the pixel parameters, and displaying the adjusted input image at the display panel. The pixel parameters include a first pixel parameter of a base luminance level of a base color channel, a first residual determined from performing inter-channel prediction, a second residual determined from performing inter-level prediction, and parameters used in the performing of the inter-level prediction.

Abstract: A system and a method for compensating pixel luminance of a display panel includes receiving compressed compensation parameters corresponding to parameter blocks of sub-pixels, receiving an input image, adjusting the input image according to the compressed compensation parameters, and displaying the adjusted input image at the display panel.

Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl

Abstract: Disclosed are a method and a system for determining threshold voltage (Vt) variations in field effect transistors (FETs), wherein multiple field effect transistors (FETs) (e.g., at least a first FET and a second FET), which are similar in design except for having different effective channel widths, can be selected for processing. Information regarding these multiple FETs (e.g., the ratio of the different effective channel widths and other information) can be acquired and used to define the relation between a standard deviation of an uncorrelated Vt variation and a difference between a first average Vt associated with the first FET and a second average Vt associated with the second FET. The relation can, depending upon the FET layouts, be used for different purposes (e.g., for characterizing the threshold voltage mismatch between a pair of adjacent essentially identical FETs on a chip or for characterizing a width scaling relation).

Abstract: The format of telecined video may be determined including a bottom field first cadence. In addition, video using 2:3:3:2 top field first can be identified. Moreover, mixed cadence videos can also be detected. In some embodiments, mixed cadence videos may be detected by calculating variances of different areas within a frame.

Abstract: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined and the conductive region is divided into layers. Relative electric currents flowing along the current flow-through axis in each layer and along the current flow-in-and-terminate axis in each layer are evaluated to determine a total resistance value for the conductive region.

Abstract: A display apparatus includes a touch controller configured to generate a touch event from a touch input, and the touch event corresponds to a first coordinate system of a first window. A touch-in-touch (TnT) display controller is coupled with the touch controller and configured to receive the touch event, and map the touch event from the first coordinate system to a second coordinate system of a second window.

Abstract: A system includes: a display panel; a touch panel; an application processor; a visual accelerator combining video images from the application processor with overlay data in accordance with touch events from the touch panel and parameters from the application processor to supply combined images to the display panel; and memory coupled to the application processor, the memory storing: a request list including acceleration requests; and instructions that, when executed by the application processor, cause the application processor to execute a device driver to: identify an active acceleration request of the acceleration requests, the active acceleration request being associated with an application executed by the application processor; determine an active screen area of the display panel using window arrangement data from a window manager executed by the application processor; generate parameters in accordance with the active acceleration request and the active screen area; and transmit the parameters to the visu

Abstract: An embodiment of the present invention provides an apparatus, comprising, a transceiver adapted for low-latency video transmissions over mmWave communications by using a slice alignment indication field in an audio/video protocol adaptation layer (A/V PAL) packet header to indicate whether a payload is aligned at a slice boundary and thus does not need parsing at a sink.

Abstract: The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.

Abstract: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined and the conductive region is divided into layers. Relative electric currents flowing along the current flow-through axis in each layer and along the current flow-in-and-terminate axis in each layer are evaluated to determine a total resistance value for the conductive region.

Abstract: An integrated input control and output rendering system for a processor-driven user device is provided. The system integrates input sensors (such as a keyboard, mouse, touchpad, camera, etc.) and output actuators (such as a display panel, speaker, robot, etc.) into a device independently of the user device and the applications running on the user device. The system includes an input logic engine to interpret input signals from various input devices together with an output rendering engine to output appropriate output signals in response to the input signals.

Abstract: An encoder includes a plurality of registers and is configured to: sequentially receive an array of coefficients, each of the coefficients being decomposed into a plurality of bits located at a plurality of corresponding bit positions of the coefficient; and concurrently operate on the plurality of bits of each of the coefficients.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways.

Abstract: A method of accumulating data by a processor in a nonvolatile memory to track use of a device. The method includes: retrieving by the processor a next datum for accumulation into a first accumulation stored in the memory, the next datum representing a next use of the device; generating by the processor a next dither offset; adding by the processor the next dither offset to the next datum to produce a first sum; dividing by the processor the first sum by a scale factor to produce a quantized datum; and adding by the processor the quantized datum to the first accumulation. The first accumulation tracks the use of the device.

Abstract: Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways.

Abstract: Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

Abstract: A method and system are disclosed. The method includes receiving a video clip including a plurality of frames. The method further includes detecting a telecine cadence of the video clip by comparing a top field and a bottom field of each of the plurality of frames. Further, based on the detected telecine cadence, the method reconstructs the video clip to an original frames-per-second (fps) value.

Abstract: Methods and systems may include an apparatus having hardware logic to allocate a set of macroblock bit budgets for a bitstream associated with a video signal. The hardware logic can also control a frame size of the bitstream based on the set of macroblock bit budgets in a single pass encode configuration. In one example, the hardware logic adjusts one or more quantization parameters of the bitstream according to the set of macroblock bit budgets.