Abstract: A system includes: an image capture device configured to capture image data from a camera system, the image data being in a first mosaic layout; an image display device configured to display the image data in a second mosaic layout; and a processor configured to receive the image data in the first mosaic layout and to supply the image data in the second mosaic layout to the display without intermediate conversion to a fully collocated image layout.

Abstract: A computer-implemented method, computer system, and computer program for modeling spatial correlations among a set of devices. A method includes: assigning a set of physical coordinates to each device in the set of devices; representing one of a process parameter or an electric parameter for each device as a sum of at least two stochastic terms, wherein the at least two stochastic terms are chosen to satisfy the spatial correlations; simulating formation of the set of devices using the physical coordinates and the at least one of the process parameter or the electric parameter; and obtaining statistical properties of the set of devices from the simulation.

Abstract: Anti-human sema4A antibodies useful in treating autoimmune diseases, cancers and other disease are provided herein. Anti-human sema4A antibodies can inhibit T cell proliferation and Th2 differentiation induced by IL-4, anti-CD3, anti-CD28 and recombinant sema4A.

Abstract: A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.

Abstract: Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

Abstract: Disclosed are a system and a method for determining merged resistance values of same-type terminals of multiple electrically connected multi-terminal semiconductor devices (e.g., field effect transistors) in a complex semiconductor structure, wherein all first terminals are connected to a first node, all second terminals are connected to a second node, and all third terminals are connected to a third node. Modified resistor networks are generated from a full resistor network including, but not limited to, a first modified resistor network with shorted second terminals and a second node; a second modified resistor network with shorted first terminals and a first node; and a third modified resistor network with first terminals and first node shorted and with the second terminals and second node shorted. Simulations are performed using the modified resistor networks and, based on the results, merged resistance values for the first, second, and third terminals are determined.

Abstract: Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers.

Abstract: Method and system for scheduling of a base station for HSUPA is provided. The method for scheduling of base station includes a method for scheduling of serving base station and a method for scheduling of non-serving base station, in which the method for scheduling of the serving base station comprises the base station generating a scheduling grant based on scheduling information SI and a happy bit transmitted from a terminal and based on a currently measured interference value, a configured threshold and associated resource information. The method for scheduling of the non serving base station comprises the base station generating a scheduling grant based on a currently measured interference value, a configured threshold and associated resource information.

Abstract: Methodologies enabling BEoL VNCAPs in ICs and resulting devices are disclosed. Embodiments include: providing a plurality of mandrel recesses extending horizontally on a substrate, each of the mandrel recesses having an identical width and being separated from another one of the mandrel recesses by an identical distance; providing a plurality of routes, each of the plurality of routes being positioned in a different one of the mandrel recesses; and providing first and second vertical segments on the substrate, the first vertical segment being connected to a set of the plurality of routes and separated from the second vertical segment, and the second vertical segment being separated from the set of routes.

Abstract: A hierarchical system and method of encoding and compressing image data, or video data including a sequence of images. In one embodiment, a line buffer is used to hold a line of an image, and as the second line of the image is read from the input data stream, 2×2 blocks of the image are transformed, e.g., by a Hadamard transform. Each transform results in a low-frequency component and three high-frequency component. The high-frequency components are encoded, e.g., using entropy coding, and sent out to the output bit stream. The low-frequency components are pushed to the line buffer. This process is continued until enough low-frequency components have been formed to complete a 2×2 block of low-frequency components, which is then transformed. The process may be repeated hierarchically for multiple layers.

Abstract: A method and device determine FET gate resistance based on both polysilicon resistance and the resistance values of wires and contacts connected to the gate node, plus the fraction of the electric current in each wire segment and in each contact and the path length of electric current in polysilicon. A new gate resistance expression (i.e., a master equation) is used for total gate resistance, which is the sum of core gate resistance and the resistance of wires and contacts connecting polysilicon and a gate node. When there are two or more paths for electric current going from polysilicon to the gate node, the total resistance also depends on the direction and path length of electric current in polysilicon, and the method and device next determine the fraction of electric current in each path by minimizing total resistance with respect to the fractions of the electric current in each path.

Abstract: The present invention is directed to a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2?C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3?H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100; c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2?C(R3)C(O)OXa?(C2H4O)b?(C3H6O)c?(C4H8O)d?—SO3—Y) where R3?H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a? is 0 to about 100; b? is 0 to about 100; c? is 0 to about 100; d? is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate

Abstract: In some embodiments, a motion estimation method and engine are provided. A motion estimation engine may, for example, compare source blocks from a source frame against reference blocks in a reference frame to find a suitable match for the source block. According to some embodiments, groups of reference blocks are compared at the same time against the source block, with search units within each group being selected for comparison simultaneously using both a fixed path navigation and an adaptive path navigation.

Abstract: A sequence of encoded data associated with a block of video is assessed to determine if: quantized coefficients of transformed residual pixel data associated with the block are equal to zero, the block was encoded using a temporal compression process, a slice that includes the block is configured to be encoded using only one reference picture list or two reference picture lists, the block is unpartitioned or was encoded in direct mode, a reference picture used to encode the block is the reference picture associated with a lowest index value on the one reference picture list, and an actual motion vector associated with the block is equal to a predicted motion vector associated with the block.

Abstract: A method of designing a layout, a design system and a computer program product for a multi-finger complementary metal oxide semiconductor (CMOS) inverter including a multi-finger N-type field effect transistor (NFET) and a multi-finger P-type field effect transistor (PFET) is disclosed. The design of the layout disposes a metallization wire connecting multiple drains of each type of MOS transistor. Analysis of an electric current in each segment of the metallization wire and of a total resistance of in all segments of the metallization wire provides an optimal location where the metallization wires for NFET drains and PFET drains are connected. The optimal wire connection location provides maximum drain current for the CMOS inverter along with a low wire capacitance between the wire and the gates of NFETs and PFETs.

Abstract: Methods for detecting HAV in a biological sample are provided, comprising amplifying a target nucleic acid comprising the sequence of HAV in a reaction mixture. The reaction mixture comprises a biological sample which may contain the target nucleic acid and set of oligonucleotides. The invention also provides kits for the detection of HAV.

Abstract: A controller is disclosed for hybrid systems providing power to an electrical power grid. The controller reduces wear on hybrid systems by having only a fast unit tuned to track fluctuations of a regulation signal in a normal mode of operation. By contrast, the slow unit does not track fluctuations in the regulation signal in the normal mode of operation, which reduces wear on the slow unit. The normal mode of operation is defined by an energy range of the fast unit. Energy band parameters associated with the energy range can be dynamically modified in order to optimize the efficiency of the hybrid system.

Abstract: There is provided herein a linear tri-block copolymer having the average formula (1): ABA??(1) wherein A is a polyalkyleneoxide unit or an aliphatic modified polyalkyleneoxide unit both of the general formula: R5O(CaH2aO)dY and wherein B is an internal polysiloxane unit of the general formula: [X(CaH2aO)bR2[SiO(R1)2]cSi(R1)2R2(OCaH2a)bX] wherein X and Y are divalent organic groups selected from a secondary amine or a tertiary amine and a ring-opened epoxide, such that when X is a ring-opened epoxide, Y is a secondary or tertiary amine, and when Y is a ring-opened epoxide, X is a secondary or tertiary amine. In addition, there is provided herein a method of making a linear tri-block copolymer having the average formula (1) and personal care and softener compositions comprising the same, specifically a hair conditioner.

Abstract: Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.