Abstract: A method for preparing Mg-RE alloys with high strength and ductility using selective laser melting (SLM) additive manufacturing technology includes the following steps of: A. preparing Mg-RE-(Zn)—Zr pre-alloyed spherical powder by gas atomization; B. molding the Mg-RE-(Zn)—Zr pre-alloyed spherical powder using SLM to obtain the Mg-RE alloys with high strength and ductility; and C. conducting heat treatment on the Mg-RE alloys prepared in step B: solid solution+aging treatment or only aging treatment The method adjusts and controls microstructure and mechanical properties of the alloys by adjusting and controlling process parameters of SLM (laser power, scanning speed, hatch spacing, spot diameter, layer thickness, interlayer rotation angle, substrate preheating temperature, partition width and overlapping area width) and process parameters of subsequent heat treatment (temperature and time) to prepare the Mg-RE-(Zn)—Zr alloys with high strength and ductility using SLM process for the first time.

Abstract: A display substrate including a drive-circuit layer and a light-emitting structure layer, a preparation method thereof, and a display device, the light-emitting structure layer includes an anode, a pixel definition layer, an organic light-emitting layer and a cathode, and an auxiliary electrode and an organic light-emitting block, arranged sequentially, the pixel definition layer includes an anode opening exposing the anode and an electrode opening exposing the auxiliary electrode, the organic light-emitting block is separated from the organic light-emitting layer, the auxiliary electrode includes the first, second and third auxiliary electrodes arranged sequentially; the cathode includes a first horizontal lapping part lapping with the first auxiliary electrode and a second sidewall lapping part lapping with the second auxiliary electrode, the thickness of the second sidewall lapping part in the direction parallel to the substrate is greater than that of the first horizontal lapping part in the direction per

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A light-emitting panel has a light-emitting area and an isolation area adjacent to the light-emitting area The light-emitting panel comprises a base substrate and a barrier structure, wherein the barrier structure is arranged on one side of the base substrate and located in the isolation area, and comprises a first isolation pattern, a second isolation pattern, a third isolation pattern and a fourth isolation pattern, which are sequentially arranged in a stacked manner, and the first isolation pattern is closer to the base substrate than the fourth isolation pattern; and an orthographic projection of the first isolation pattern on the substrate is located in an orthographic projection of the second isolation pattern on the base substrate, and an orthographic projection of the third isolation pattern on the base substrate is located in an orthographic projection of the fourth isolation pattern on the base substrate.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: An epitaxial structure adapted to a semiconductor pickup element is provided. The semiconductor pickup element has at least one guiding structure and provided with a pickup portion. The epitaxial structure includes a semiconductor layer corresponding to the pickup portion and capable of being picked up by the semiconductor pickup element. The epitaxial structure also includes at least one alignment structure disposed on the semiconductor layer and corresponding to the at least one guiding structure, so that the epitaxial structure and the semiconductor pickup element are positioned relative to each other. The number of the at least one alignment structure matches the number of the at least one guiding structure.

Abstract: This disclosure describes one or more implementations of a digital image semantic layout manipulation system that generates refined digital images resembling the style of one or more input images while following the structure of an edited semantic layout. For example, in various implementations, the digital image semantic layout manipulation system builds and utilizes a sparse attention warped image neural network to generate high-resolution warped images and a digital image layout neural network to enhance and refine the high-resolution warped digital image into a realistic and accurate refined digital image.

Abstract: Methods, system and apparatus for relieving pressure in an organ such as, but not limited to, the eye are disclosed. The method includes implanting a bioabsorbable channel into the selected area of the organ using a delivery apparatus.

Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

Abstract: The invention relates to a system and a method for using a trusted device to browse e-books. The system comprises an author end, a user end, an electronic bookstore unit, and a data storage unit. In the cloud system, an e-book author can set the authorization mechanism about e-book sale and downloading to protect their copyrights and to upload the e-book by the electronic bookstore unit. The user also can browse e-books by assigned electronic apparatuses to protect purchase rights from being illegally copied. The e-book is an encrypted file, so the user has to use the identification code of the certified electronic apparatus as a decrypted key to decrypt the e-book file for reading.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.