Abstract: Provided are an intelligent safety monitoring system and method. The intelligent safety monitoring system includes: a monitoring unit configured to monitor status information of a vehicle; a control unit connected to the monitoring unit and configured to determine, based on the status information of the vehicle, whether an abnormality occurs on the vehicle; a camera unit connected to the control unit and configured to obtain surrounding environment information of the vehicle based on a control instruction output by the control unit when the control unit determines that the abnormality occurs; and a mobile terminal communicatively connected to the control unit and configured to receive and output the status information of the vehicle and/or an abnormality determination result and the surrounding environment information that are sent by the control unit.

Abstract: A method for preparing Mg-RE alloys with high strength and ductility using selective laser melting (SLM) additive manufacturing technology includes the following steps of: A. preparing Mg-RE-(Zn)—Zr pre-alloyed spherical powder by gas atomization; B. molding the Mg-RE-(Zn)—Zr pre-alloyed spherical powder using SLM to obtain the Mg-RE alloys with high strength and ductility; and C. conducting heat treatment on the Mg-RE alloys prepared in step B: solid solution+aging treatment or only aging treatment The method adjusts and controls microstructure and mechanical properties of the alloys by adjusting and controlling process parameters of SLM (laser power, scanning speed, hatch spacing, spot diameter, layer thickness, interlayer rotation angle, substrate preheating temperature, partition width and overlapping area width) and process parameters of subsequent heat treatment (temperature and time) to prepare the Mg-RE-(Zn)—Zr alloys with high strength and ductility using SLM process for the first time.

Abstract: A method for preparing Mg-RE alloys with high strength and ductility using selective laser melting (SLM) additive manufacturing technology includes the following steps of: A. preparing Mg-RE-(Zn)—Zr pre-alloyed spherical powder by gas atomization; B. molding the Mg-RE-(Zn)—Zr pre-alloyed spherical powder using SLM to obtain the Mg-RE alloys with high strength and ductility; and C. conducting heat treatment on the Mg-RE alloys prepared in step B: solid solution+aging treatment or only aging treatment The method adjusts and controls microstructure and mechanical properties of the alloys by adjusting and controlling process parameters of SLM (laser power, scanning speed, hatch spacing, spot diameter, layer thickness, interlayer rotation angle, substrate preheating temperature, partition width and overlapping area width) and process parameters of subsequent heat treatment (temperature and time) to prepare the Mg-RE-(Zn)—Zr alloys with high strength and ductility using SLM process for the first time.

Abstract: This disclosure describes one or more implementations of a digital image semantic layout manipulation system that generates refined digital images resembling the style of one or more input images while following the structure of an edited semantic layout. For example, in various implementations, the digital image semantic layout manipulation system builds and utilizes a sparse attention warped image neural network to generate high-resolution warped images and a digital image layout neural network to enhance and refine the high-resolution warped digital image into a realistic and accurate refined digital image.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer.

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract: A fixing device for a planar display panel includes a fastening fixture for fixing the planar display panel on a carrier stage in which a plurality of slide slots are provided. The fastening fixture includes a driving rod capable of being inserted into one of the slide slots, a fixture body and a bottom plate. The driving rod is connected with the fixture body and the bottom plate, which are respectively provided on two sides of the carrier stage in operation, and a spring is wound around the driving rod and capable of driving the bottom plate to move.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.