Patents by Inventor Ning Su
Ning Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8592859Abstract: Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer.Type: GrantFiled: May 27, 2009Date of Patent: November 26, 2013Assignee: University of Notre Dame du LacInventors: Patrick Fay, Ning Su
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Patent number: 8558313Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: March 21, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Patent number: 8464991Abstract: A fixing device for a planar display panel includes a fastening fixture for fixing the planar display panel on a carrier stage in which a plurality of slide slots are provided. The fastening fixture includes a driving rod capable of being inserted into one of the slide slots, a fixture body and a bottom plate. The driving rod is connected with the fixture body and the bottom plate, which are respectively provided on two sides of the carrier stage in operation, and a spring is wound around the driving rod and capable of driving the bottom plate to move.Type: GrantFiled: March 25, 2010Date of Patent: June 18, 2013Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.Inventor: Ning Su
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Patent number: 8450779Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.Type: GrantFiled: March 8, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Hen, Chung-Hsun Lin, Ning Su
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Patent number: 8377980Abstract: The present disclosure relates to compounds, compositions and methods for the treatment of Hepatitis C virus (HCV) infection. Also disclosed are pharmaceutical compositions containing such compounds and methods for using these compounds in the treatment of HCV infection.Type: GrantFiled: December 1, 2010Date of Patent: February 19, 2013Assignee: Bristol-Myers Squibb CompanyInventors: Makonen Belema, Jeffrey Lee Romine, Van N. Nguyen, Gan Wang, Omar D. Lopez, Denis R. St. Laurent, Qi Chen, John A. Bender, Zhong Yang, Piyasena Hewawasam, Ningning Xu, Nicholas A. Meanwell, John A. Easter, Bao-Ning Su, Michael J. Smith
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Publication number: 20120329193Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Publication number: 20120295423Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.Type: ApplicationFiled: July 25, 2012Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Publication number: 20120197175Abstract: The invention generally relates to shunts in which at least a portion of the body includes a drug.Type: ApplicationFiled: December 8, 2011Publication date: August 2, 2012Applicant: AQUESYS, INC.Inventors: Christopher Horvath, Ronald D. Bache, Laszlo O. Romoda, Dao-Yi Yu, Cory Anderson, Roelof Trip, Ying Yang, Hoang Van Nguyen, Surag Mantri, Er-Ning Su, Stephen Cringle, James McCrea, Daniel Mufson, Colin Tan, Richard L. Lindstrom
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Patent number: 8232599Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: January 7, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20120187492Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: ApplicationFiled: March 21, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20120112310Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8138547Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.Type: GrantFiled: August 26, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8105893Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.Type: GrantFiled: November 18, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8076488Abstract: This invention relates to novel diaryl ureas, pharmaceutical compositions containing such compounds and the use of those compounds or compositions for treating hyper-proliferative and angiogenesis disorders, as a sole agent or in combination with cytotoxic therapies.Type: GrantFiled: March 1, 2004Date of Patent: December 13, 2011Assignee: Bayer Healthcare LLCInventors: Jacques Dumas, Stephen Boyer, Sharad Verma, Lila Adnane, Yuanwei Chen, Wendy Lee, Barton Phillips, Roger A. Smith, William J. Scott, Jennifer Burke, Jianqing Chen, Zhi Chen, Jianmei Fan, Karl Miranda, Brian Raudenbush, Aniko Redman, Jianxing Shao, Ning Su, Gan Wang, Lin Yi, Qingming Zhu
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Publication number: 20110286961Abstract: The present disclosure relates to compounds, compositions and methods for the treatment of Hepatitis C virus (HCV) infection. Also disclosed are pharmaceutical compositions containing such compounds and methods for using these compounds in the treatment of HCV infection.Type: ApplicationFiled: December 1, 2010Publication date: November 24, 2011Inventors: Makonen Belema, Jeffrey Lee Romine, Van N. Nguyen, Gan Wang, Omar D. Lopez, Denis R. St. Laurent, Qi Chen, John A. Bender, Zhong Yang, Piyasena Hewawasam, Ningning Xu, Nicholas A. Meanwell, John A. Easter, Bao-Ning Su, Michael J. Smith
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Publication number: 20110263597Abstract: Methods of treating a mammal having a condition characterized by abnormal angiogenesis or hyperpermiability processes using substituted pyridazines having angiogenesis inhibiting activity and the generalized structural formula wherein the ring containing A, B, D, E, and L is phenyl or a nitrogen-containing heterocycle; groups X and Y may be any of a variety of defined linking units; R1 and R2 may be defined independent substituents or together may be a ring-defining bridge; ring J may be an aryl, pyridyl, or cycloalkyl group; and G groups may be any of a variety of defined substituents.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: Bayer HealthCare LLCInventors: Jacques P. Dumas, Stephen James Boyer, Julie A. Dixon, Teddy Kite Joe, Harold C. E. Kluender, Wendy Lee, Dhanapalan Nagarathnam, Robert N. Sibley, Ning Su
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Publication number: 20110227043Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8017483Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.Type: GrantFiled: June 29, 2009Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Nivo Rovedo, Werner A. Rausch, Jian Yu
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Publication number: 20110215300Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.Type: ApplicationFiled: March 8, 2010Publication date: September 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su
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Patent number: 8013166Abstract: This invention relates to certain aryl alkyl acid compounds, compositions, and methods for treating or preventing obesity and related diseases.Type: GrantFiled: September 5, 2008Date of Patent: September 6, 2011Assignee: Bayer Healthcare LLCInventors: Roger A. Smith, Ann-Marie Campbell, Philip Coish, Miao Dai, Susan Jenkins, Derek Lowe, Stephen J. O'Connor, Ning Su, Gan Wang, Mingbao Zhang, Lei Zhu