Abstract: Described herein are systems and techniques for implementing a petrophysics assistant. An example method can include receiving, by a control language model configured to perform natural language processing, a query related to one or more subject areas; based on the one or more subject areas associated with the query and a respective domain-specific knowledge of each domain-specific language model from a plurality of domain-specific language models, selecting one or more domain-specific language models from the plurality of domain-specific language models to answer the query; sending, to the one or more domain-specific language models, a request to answer the query; and generating, by the control language model, a response to the query based on one or more responses to the query received from the one or more domain-specific language models.

Abstract: The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: A system can receive downhole acquisition data relating to a wellbore. The system can pre-process the downhole acquisition data. The system can generate an incomplete borehole image using the downhole acquisition data. The system can determine a sparse representation based on the incomplete borehole image by performing an optimization with respect to the incomplete borehole image. The system can generate a complete borehole image based on an inverse of the sparse representation.

Abstract: Disclosed herein are a solder alloy composition comprising Sn—Bi—In base solder particles. The Sn—Bi—In base solder particles is characterized by having an average diameter less than 10 ?m, and the Sn—Bi—In base alloy comprises 12-22% of Sn, 33-43% of Bi and 45-55% by weight. Also disclosed herein is a method for producing the Sn—Bi—In base solder particles. The method mainly includes the steps of, sintering a mixture comprising tin (Sn), bismuth (Bi) and indium (In) at a designated weight ratio to produce a bulk alloy; dissolving the bulk alloy to produce an alloy solution; and subjected the alloy solution to ultrasonication at a first temperature of about 65-85° C. and then cooling at a second temperature of about 0-25° C., thereby produces the present Sn—Bi—In base solder particles.

Abstract: A porous copper-based filter material that is electrodeposited with nanotwin copper to provide anti-pathogenic properties, particularly against Covid-19 or the SARS virus. The nanotwin copper is a thin layer of (111) oriented nanotwin copper microstructure.

Abstract: The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Abstract: An auxiliary prediction system is provided to predict reliability of an object after a specific operation is applied to the target object. The auxiliary prediction system includes an image correction module and an analysis module. The image correction module performs an image correction procedure to convert an original image of the target object into a first correction image. The analysis module performs a feature analysis on the first correction image through an artificial intelligence model that has been trained, so as to predict whether the target object has a defect or not after the specific operation.

Abstract: A system can receive downhole acquisition data relating to a wellbore. The system can pre-process the downhole acquisition data. The system can generate an incomplete borehole image using the downhole acquisition data. The system can determine a sparse representation based on the incomplete borehole image by performing an optimization with respect to the incomplete borehole image. The system can generate a complete borehole image based on an inverse of the sparse representation.

Abstract: An auxiliary prediction system is provided to predict reliability of an object after a specific operation is applied to the target object. The auxiliary prediction system includes an image correction module and an analysis module. The image correction module performs an image correction procedure to convert an original image of the target object into a first correction image. The analysis module performs a feature analysis on the first correction image through an artificial intelligence model that has been trained, so as to predict whether the target object has a defect or not after the specific operation.

Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.

Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.

Abstract: A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.

Abstract: In an anisotropic flexible thermal interface pad, a heat-conduction layer on a dielectric layer is formed by using electroflocking to attach a plurality of thermally-conductive fibers, such as carbon fibers, on the dielectric layer and sealing the fibers with a sealing agent, such as silicone. The sealing agent is less thermally-conductive than the fibers. The plurality of fibers is aligned substantially-unidirectionally to achieve a predetermined inclination angle (e.g., 90°) with respect to the dielectric layer for discouraging neighboring fibers to contact each other while maintaining efficient heat transmission along each fiber. Thus, heat is transmitted more efficiently along a direction perpendicular to the dielectric layer than along another direction in parallel thereto. The pad may include additional heat-conduction layers, each configured similar to the heat-conduction layer, stacked together thereon.

Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.

Abstract: The present application provides a lithium ion battery including a thermal sensitive layer comprising polymer particles. The thermal sensitive layer may be disposed between the electrodes and the separator. When the lithium ion battery is under thermal runaway condition and the internal temperature rises to a critical temperature, the polymer particles undergo a thermal transition process (melting) to form an insulating barrier on the electrodes, which blocks lithium ion transfer between the electrodes and shuts down the internal current of the battery.

Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.

Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.