Abstract: The present invention relates to a specimen box for an electron microscope, comprising a first substrate, a second substrate, one or more photoelectric elements, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through holes penetrate through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. The photoelectric element is disposed between the first substrate and the second substrate. In addition, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen contained therein. Besides, the present specimen box further comprises one or more plugs. When the plugs are assembled into the first through holes to seal the specimen box, the in-situ observation can be accomplished by using the electron microscope.

Abstract: The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.

Abstract: The present invention relates to a specimen box for an electron microscope, comprising a first substrate, a second substrate, one or more photoelectric elements, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through holes penetrate through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. The photoelectric element is disposed between the first substrate and the second substrate. In addition, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen contained therein. Besides, the present specimen box further comprises one or more plugs. When the plugs are assembled into the first through holes to seal the specimen box, the in-situ observation can be accomplished by using the electron microscope.

Abstract: The present invention relates to a specimen box for an electron microscope, which comprises a first substrate, a second substrate, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through hole penetrates through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. Besides, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen placed therein. In addition, the specimen box of the present invention further comprises one or more plugs. When the plug is assembled into the first through hole to seal the specimen box, the in-situ observation can be accomplished by using an electron microscope.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: Devices for fabricating oriented polymer fibers, and methods for fabricating thereof by electropulling, are provided.

Abstract: An electrical lead for an electronic device has a core conductor and a finishing layer of a Sn alloy deposited on a surface of the core conductor of the electrical lead. The finishing layer of the Sn alloy deposited on the surface of the core conductor is of a chemical composition that hinders the formation of Sn whiskers. An electronic device has such an electrical lead.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: The present invention is a method of fabricating a self-peeling nickel foil from a silicon wafer. The method includes forming a template of silicon by electrochemically etching a portion of the Si wafer to create a porous Si portion with pores of a desired depth. Then electrolessly plating nickel into the template, wherein the porous silicon portion is converted into a porous nickel portion and continuing the electroless plating until the internal tensile stress at an interface of the porous nickel portion and the silicon wafer is great enough to self-peel the porous nickel portion from the silicon wafer creating a nickel foil.

Abstract: This invention provides a process for protecting solder joints, comprising forming an UBM or pad metallurgy in solder joints and then further forming a small solder bump on UBM or pad metallurgy between substrate and chip. Wherein a material of high electric resistance is coated at the ends of UBM or pad metallurgy where substrate is connected to chip, as to equalize the current distribution of solder bump, therefore the electromigration resistance of solder joints is improved by suppressing the current crowding and joule heating phenomenon.

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Abstract: An improved dielectric material having pores formed therein and a method for forming the material are disclosed. The material is formed of a polymer. Pores within the polymer are formed by forming solid organic particles within the polymer and eventually vaporizing the particles to form pores within the polymer.

Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: Dopant activation in heavily boron doped p.sup.+ --Si is achieved by applying electric current of high density. The p.sup.+ --Si was implanted by a 40 KeV BF.sup.2+ at an ion intensity 5.multidot.10.sup.15 ions per cm.sup.2 and annealed at 900.degree. C. for 30 minutes to obtain a partial boron activation according to conventional processing steps. To obtain additional activation and higher conductivity, current was gradually applied according to the invention to a current density of approximately 5.times.10.sup.6 A/cm.sup.2 was realized. The resistance of the p.sup.+ --Si gradually increases and then decreases with a precipitous drop at a threshold current. The resistance was reduced by factor of 5 to 18 times and was irreversible if an activation current threshold was reached or exceeded. The high-current-density-dopant activation occurs at room temperature.

Abstract: In the design of stud and conducting line joints, the conducting line is extended beyond the stud without any significant overhang of the line in the width direction for minimizing induced stress in order to reduce voids and crack growth in the region where the connecting line is joined to the stud. The preferred length of the extension is in the range approximately between one-quarter and twice the stud dimension. The design is applicable, but not limited to, multilevel integrated circuits used in computers and other electrical devices.

Abstract: An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.

Abstract: An apparatus and method for forming an interconnect through an opening or on an insulation layer with the coefficient of thermal expansion of the interconnect adjusted to reduce the thermal stress between the interconnect and the insulation layer is described incorporating the steps of forming a solid solution of a binary alloy including germanium and aluminum or a ternary alloy including aluminum, germanium and a third element, for example silicon, and forming a precipitate from the solid solution at a reduced temperature with respect to the temperature of forming the solid solution whereby the volume of the precipitate including germanium and the remaining solid solution is larger than the volume of the original solid solution.

Abstract: An improved thin film barrier with three layers where an interlayer is between barrier layers on each side, the interlayer serving as an atom energy sink. The improved barrier in the diffusion of Cu through Ni into Au where the barrier layers are Ni and the interlayer is Au, making a stack of AuNiAuNiCu, reduces the Cu present in the external Au layer after prolonged annealing in the vicinity of 0.2% atomic.