Abstract: A utility post is provided that includes a first flange, a second flange, and a rib. The first flange resides in a plane and the second flange resides in the same plane. The rib is perpendicular to the plane. First, second, and third apertures are also provided, the first aperture defined through the first flange, the second aperture defined through the second flange, and the third aperture defined through the rib.

Abstract: Disclosed herein is a comb sensor for measuring combing resistance, wherein the comb sensor comprises: a comb or brush comprising a handle, a head connected to the handle, and teeth connected to the head; and a bend sensor located on at least one of the teeth, to measure the bending of the one of the teeth. The present invention provides improved sensitivity and/or detailed measurement result.

Abstract: A rackable fence is provided with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: A sensing device comprising a first array of electrodes encapsulated in a first elastomeric layer; a second array of electrodes encapsulated in a second elastomeric layer; a third elastomeric layer intermediate the first and second elastomeric layer and comprising an array of micro-structures, wherein said electrodes and elastomeric layers are configured such that a displacement of said micro-structures, in response to one or more forces and/or pressures applied to said device, causes a capacitance of said device to vary as a function of said forces and/or pressure applied.

Abstract: A rackable fence is provided with a rail; picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: A rackable fence is provided with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: A rackable fence is provided with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: A rackable fence with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: A rackable fence with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.

Abstract: Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit (“IC”) is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned.

Abstract: On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.

Abstract: Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.

Abstract: One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak data, for example, allele peak area, allele peak height and optical density, derived/obtained from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.

Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak data derived obtained from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.