Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak area derived from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.

Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

Abstract: A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programmable logic portion. The programmable logic portion is used for such tasks as synchronizing the byte-aligned data in accordance with any one of a number of possible data communication protocols.

Abstract: The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.

Abstract: A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

Abstract: Methods and systems for determining the correlation between electronic informational campaigns, for example, two advertising campaigns by a two phase process, based on the behavior of multiple users. In a first phase, probabilities of one campaign, with respect to another campaign, are calculated, and values of expected revenue for each campaign are determined from the probabilities. The campaigns with the greatest expected revenues are then analyzed, to determine the extent of their correlation, in the second phase. In the second phase, the correlation between two campaigns is determined, by determining a correlation value, indicative of the correlation between two campaigns.

Abstract: An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.

Abstract: A data converter for a padded protocol interface performs, on a first data sample, decoding operations requiring data from second and third data samples, while buffering the second data sample without buffering the third data sample. A state machine controlling the decoding operation waits an additional clock cycle, until the second sample has become the current sample and the third sample has become the second sample and thus is available.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak data derived obtained from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.

Abstract: Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.

Abstract: A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak area derived from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: A method and apparatus for reducing block related artifacts in video are disclosed. A boundary is defined in a video frame between at least two or more sub-blocks where each of the sub-blocks contains a predetermined number of pixels. Pixels adjacent to the boundaries of the sub-blocks may be filtered to reduce blocking artifacts in the video. Pixel video values such as luma and chroma values may be utilized as input values to an anti-block filter. Average mean and average variance of the pixel video values in a sub-block are used to determined when anti-block filtering is applied. Pixels adjacent to the sub-block boundaries are filtered with an anti-block filtering algorithm in the event a predetermined condition is satisfied where the condition may be based upon the calculated average mean and average variance values. The filtering algorithm may include recalculating a pixel video value for pixels adjacent the sub-block boundaries.

Abstract: Least Square Deconvolution (LSD) uses quantitative allele peak data derived obtained from a sample containing the DNA of more than one contributor to resolve the best-fit genotype profile of each contributor. The resolution is based on finding the least square fit of the mass ratio coefficients at each locus to come closest to the quantitative allele peak data. Consistent top-ranked mass ratio combinations from each locus can be pooled to form at least one composite DNA profile at a subset of the available loci. The top-ranked DNA profiles can be used to check against the profile of a suspect or be used to search for a matching profile in a DNA database.

Abstract: A circuit for freezing a video frame having a first field interlaced with a second field. The circuit generally comprises a memory and a filter. The memory may be configured to present a plurality of coefficient signals that define (i) a first coefficient set for the first field and (ii) a second coefficient set for the second field. The filter may be configured to present a new frame in place of the video frame. The new frame may be generated from either (i) the first field and the first coefficient set in response to freezing on the first field or (ii) the second field and the second coefficient set in response to freezing on the second field.