Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: A video presentation system including a single physical computing device, a video capture device in communication with the physical computing device; and a computer readable medium readable by the physical computing device and including a video capture code segment for reading a video signal comprising a first plurality of pixels from the video capture device and storing the first set of pixels a buffer, an desktop capture code segment for capturing a content of a desktop of physical computing device and storing the content of the desktop in a buffer, and a chroma key code segment for setting a color value for a pixel in a buffer equal based on the color information of another pixel in another buffer.

Abstract: A cross-connect switching system includes a plurality of three stage switching arrays and an expansion switching array, wherein a second stage of each of the three stage switching arrays includes an expansion section comprising switches which facilitate interconnection of each three stage array to the expansion switching array. In one embodiment, the expansion switching array includes a plurality of square arrays, each having Q inputs and Q outputs and wherein the second stages of the three stage arrays each include 1 . . . M+1 . . . M+p vertical stages which connect to the square “D” arrays of the central expansion switching array.

Abstract: The present invention provides a method for eliciting an onset hastened analgesic and anti-inflammatory response and combating nausea in acute migraine attacks. This method comprises administering a pharmaceutical composition comprising more than one active ingredient, wherein said more than one active ingredient consist essentially of: (i) domperidone or an analogue thereof in an amount sufficient to hasten the onset of the analgesic and anti-inflammatory response and to combat nausea in an acute migraine attack, and (ii) a NSAID, a pharmaceutically acceptable salt thereof or a pure (?) or pure (+) optical isomeric form thereof in an analgesically and anti-inflammatory effective amount, wherein said NSAID is selected from the group consisting of proprionic acid derivatives, acetic acid derivatives, fenamic acid derivatives, biphenylcarboxylic acid derivatives and oxicams.

Abstract: Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

Abstract: A radio frequency (RF) front-end configured to share transmissions and receptions of Bluetooth signals and WLAN signals. In an exemplary embodiment, the RF front-end comprises a first path coupled between an antenna and a transceiver dedicated to transmissions of the WLAN signals; a second path coupled between the antenna and the transceiver dedicated to simultaneous receptions of the Bluetooth signals and the WLAN signals; and a third path coupled between the antenna and the transceiver. The third path may be dedicated to transmissions only of the Bluetooth signals when a WLAN link is active; and transmissions and receptions of the Bluetooth signals when the WLAN link is active and in a power save state, and when the WLAN link is inactive.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: An instant beverage product includes a disposable cup, a soluble ingredient disposed in a bottom portion of the disposable cup, and a sealing layer sealed at an inner surface of the disposable cup at the bottom portion thereof to seal and enclose the soluble ingredient in said disposable cup, wherein the sealing layer is removed from said disposable cup for a predetermined volume of water being added into the disposable cup to mix with the soluble ingredient to form an instant beverage. The instant beverage product is adapted to be stacked up with another instant beverage product when the bottom portion of said disposable cup is placed in the upper portion of another disposable cup through the top opening thereof to minimize a space for packing two or more the instant beverage products together.

Abstract: A cross-connect switching system includes a plurality of three stage switching arrays and an expansion switching array, wherein a second stage of each of the three stage switching arrays includes an expansion section comprising switches which facilitate interconnection of each three stage array to the expansion switching array. In one embodiment, the expansion switching array includes a plurality of square arrays, each having Q inputs and Q outputs and wherein the second stages of the three stage arrays each include 1 . . . M+1 . . . M+p vertical stages which connect to the square “D” arrays of the central expansion switching array.

Abstract: Software is employed to create an array of switch identifiers based on a known switching system architecture. A switch identifier array is preferably determined and stored in the system as part of the system manufacturing process prior to deployment of the system at an end user site. A relatively straight forward indexing operation may then be used to determine those sets of switches which are available to establish a desired interconnection, greatly simplifying selection of appropriate switches to create a desired path during real time operation of a deployed system.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: Disclosed herein are systems and methods for applying unified management policies to monitor, store, search and otherwise manage electronic communications, no matter what format those electronic communications take. Such unified management policy or policies are based on an integrated true identity of a user, typically a person. In one embodiment, a policy implementation module for managing electronic communications transmitted across a communications network in multiple communication formats is provided. The module comprises a message filtering process configured to uniformly filter electronic communications transmitted in the multiple communication formats and that are determined to be associated with a true identity of user employing the multiple communication formats.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.