Abstract: A medical device monitor (MedMon), method and computer readable medium is disclosed. The MedMon is configured to operate in a system having communications between a first medical device associated with a patient and a second device. The MedMon includes a receiver configured to snoop on communications between the first medical device and second device. An anomaly detector having a set of security polices is configured to detect an anomaly by analyzing the communications between the first medical device and second device for compliance with the security policies. A response generator configured to generate a response on a condition that an anomaly is detected. The response may be a warning message configured to warn the patient. The MedMon may include a transmitter configured to transmit the response. The response may be a jamming signal configured to disrupt communications between the first medical device and second device.

Abstract: Embodiments of the application provide device, method and system for routing global assistant signals in a NoC. The device comprises: a signal distributing element having an associated intermediate router provided in a system for routing global assistant signals in a NoC which includes at least one intermediate router electrically interposed between a source router and a destination router, wherein the signal distributing element is configured to: based on a predetermined criterion, select either local global assistant signals generated by the associated intermediate router or upstream global assistant signals received from an upstream router of the associated intermediate router as current global assistant signals to be sent to a downstream router of the associated intermediate router.

Abstract: According to various embodiments, a stress detection and alleviation (SoDA) system for a user is disclosed. The system includes a SoDA device configured with one or more processors that receive wearable medical sensor (WMS) data from a plurality of WMSs. The processors are programmed to remove one or more artifacts from the WMS data, extract a set of features from the WMS data, remove correlated features from the extracted features to obtain a reduced set of features, classify the reduced set of features in order to determine whether the user is stressed, and generate a response based on whether the user is stressed.

Abstract: An implantable medical device (IMD) configured to communicate with an external device (ED). The ED supports two way RF communications and has a light source. The IMD includes a processor coupled to an optical detector, the processor is configured to verify that light is being received from the ED light source and that the ED is a trusted device, establishing a unidirectional optical channel from the ED to the IMD. An RF transceiver is coupled to the processor, the processor being configured permit two way RF communications with the ED only under a condition that the ED is verified as a trusted device. The processor may be configure to wake up periodically or aperiodically to check for the presence of light from the ED light source. The processor may be configured to detect a multi-bit message from the ED via the unidirectional optical channel. The multi-bit message may include a key.

Abstract: According to some embodiments, a system for securing communications between an implantable wearable medical device (IWMD) and an external device (ED) is disclosed. The system includes a wireless radio frequency (RF) channel configured for communication between the IWMD and the ED. The system further includes a vibration-based side channel configured for verifying communication between the IWMD and the ED such that the RF channel is activated only when the IWMD detects a vibration signal generated by an ED.

Abstract: A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.

Abstract: A user authentication system for an electronic device for use with a plurality of wireless wearable medical sensors (WMSs) and a wireless base station that receives a biomedical data stream (biostream) from each WMS. The system includes a BioAura engine located on a server, the server has a wireless transmitter/receiver with receive buffers that store the plurality of biostreams, the biostream from a single WMS lacks the discriminatory power to identify the user, the BioAura engine has a look up stage and a classifier, the classifier generates an authentication output based on the plurality of biostreams, the authentication output authenticates the user's access to the electronic device. The wireless base station has a transmitter/receiver having receive buffers that store the biomedical data from each WMS, the wireless base station has a communication engine that retrieves the biostream from each WMS and transmits the plurality of biostreams to the server.

Abstract: An implantable/wearable medical device is configured for use with a plurality of sensors. The device includes a host microcontroller, a safety coprocessor and an actuator. The host microcontroller is configured to receive physiological data from the sensors and generate actuator commands for the actuator. The host microcontroller is configured to generate program state data for transmission to the safety coprocessor. The safety coprocessor is configured to receive the physiological data from the sensors and I/O access data and the program state information from the host microcontroller and determine whether there is a safety rule violation. The safety coprocessor is also configured to issue the actuator command to the actuator if no safety rule violation is detected. The safety coprocessor is also configured to initiate safety procedures if a safety rule violation is detected.

Abstract: A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic.

Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.

Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.

Abstract: A medical device monitor (MedMon), method and computer readable medium is disclosed. The MedMon is configured to operate in a system having communications between a first medical device associated with a patient and a second device. The MedMon includes a receiver configured to snoop on communications between the first medical device and second device. An anomaly detector having a set of security polices is configured to detect an anomaly by analyzing the communications between the first medical device and second device for compliance with the security policies. A response generator configured to generate a response on a condition that an anomaly is detected. The response may be a warning message configured to warn the patient. The MedMon may include a transmitter configured to transmit the response. The response may be a jamming signal configured to disrupt communications between the first medical device and second device.

Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.

Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.

Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.

Abstract: A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.

Abstract: A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit.

Abstract: Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives.