Patents by Inventor Niraj K. Jha

Niraj K. Jha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735783
    Abstract: A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: August 15, 2017
    Assignee: THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Ting-Jung Lin, Wei Zhang, Niraj K. Jha
  • Publication number: 20170230360
    Abstract: A user authentication system for an electronic device for use with a plurality of wireless wearable medical sensors (WMSs) and a wireless base station that receives a biomedical data stream (biostream) from each WMS. The system includes a BioAura engine located on a server, the server has a wireless transmitter/receiver with receive buffers that store the plurality of biostreams, the biostream from a single WMS lacks the discriminatory power to identify the user, the BioAura engine has a look up stage and a classifier, the classifier generates an authentication output based on the plurality of biostreams, the authentication output authenticates the user's access to the electronic device. The wireless base station has a transmitter/receiver having receive buffers that store the biomedical data from each WMS, the wireless base station has a communication engine that retrieves the biostream from each WMS and transmits the plurality of biostreams to the server.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 10, 2017
    Applicants: The Trustees of Princeton University, PURDUE RESEARCH FOUNDATION, Indian Statistical Institute
    Inventors: Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
  • Publication number: 20170213002
    Abstract: An implantable/wearable medical device is configured for use with a plurality of sensors. The device includes a host microcontroller, a safety coprocessor and an actuator. The host microcontroller is configured to receive physiological data from the sensors and generate actuator commands for the actuator. The host microcontroller is configured to generate program state data for transmission to the safety coprocessor. The safety coprocessor is configured to receive the physiological data from the sensors and I/O access data and the program state information from the host microcontroller and determine whether there is a safety rule violation. The safety coprocessor is also configured to issue the actuator command to the actuator if no safety rule violation is detected. The safety coprocessor is also configured to initiate safety procedures if a safety rule violation is detected.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 27, 2017
    Applicant: The Trustees of Princeton University
    Inventors: Niraj K. Jha, Younghyun Kim, Vijay Raghunathan, Anand Raghunathan
  • Publication number: 20150381182
    Abstract: A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic.
    Type: Application
    Filed: December 4, 2013
    Publication date: December 31, 2015
    Applicant: The Trustees of Princeton University
    Inventors: Ting-Jung LIN, Wei ZHANG, Niraj K. JHA
  • Patent number: 9099195
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 4, 2015
    Assignee: The Trustees of Princeton University
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Patent number: 8990740
    Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: March 24, 2015
    Assignee: The Trustees of Princeton University
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Publication number: 20140059282
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Application
    Filed: December 7, 2011
    Publication date: February 27, 2014
    Inventors: Wei ZHANG, Niraj K. JHA, Li SHANG
  • Publication number: 20130247194
    Abstract: A medical device monitor (MedMon), method and computer readable medium is disclosed. The MedMon is configured to operate in a system having communications between a first medical device associated with a patient and a second device. The MedMon includes a receiver configured to snoop on communications between the first medical device and second device. An anomaly detector having a set of security polices is configured to detect an anomaly by analyzing the communications between the first medical device and second device for compliance with the security policies. A response generator configured to generate a response on a condition that an anomaly is detected. The response may be a warning message configured to warn the patient. The MedMon may include a transmitter configured to transmit the response. The response may be a jamming signal configured to disrupt communications between the first medical device and second device.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Inventors: Niraj K. Jha, Anand Raghunathan, Meng Zhang
  • Publication number: 20130135008
    Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.
    Type: Application
    Filed: December 1, 2010
    Publication date: May 30, 2013
    Applicants: TRUSTEES OF PRINCETON UNIVERSITY, QUEEN'S UNIVERSITY AT KINGSTON
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Patent number: 8117436
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 14, 2012
    Assignees: Queen's University at Kingston, Trustees of Princeton University
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Publication number: 20090219051
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Application
    Filed: April 19, 2007
    Publication date: September 3, 2009
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Patent number: 7278123
    Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: October 2, 2007
    Assignee: NEC Laboratories America, Inc.
    Inventors: Srivaths Ravi, Anand Raghunathan, Loganathan Lingappan, Srimat Chakradhar, Niraj K Jha
  • Patent number: 7260809
    Abstract: A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 21, 2007
    Assignee: NEC Laboratories America, Inc.
    Inventors: Srivaths Ravi, Anand Raghunathan, Lin Zhong, Niraj K. Jha
  • Patent number: 6308313
    Abstract: A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventors: Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha
  • Patent number: 6289488
    Abstract: Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 11, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Bharat P. Dave, Niraj K. Jha
  • Patent number: 6195786
    Abstract: A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: February 27, 2001
    Assignees: NEC USA, Inc., Princeton University
    Inventors: Anand Raghunathan, Sujit Dey, Ganesh Lakshminarayana, Niraj K. Jha
  • Patent number: 6117180
    Abstract: Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 12, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Bharat P. Dave, Niraj K. Jha
  • Patent number: 6110220
    Abstract: Hardware-software co-synthesis of an embedded system requires mapping of its specifications into hardware and software modules such that its real-time and other constraints are met. Embedded system specifications are generally represented by acyclic task graphs. Many embedded system applications are characterized by aperiodic as well as periodic task graphs. Aperiodic task graphs can arrive for execution at any time and their resource requirements vary depending on how their constituent tasks and edges are allocated. Traditional approaches based on a fixed architecture coupled with slack stealing and/or on-line determination of how to serve aperiodic task graphs are not suitable for embedded systems with hard real-time constraints, since they cannot guarantee that such constraints would always be met. The present invention addresses the problem of concurrent co-synthesis of aperiodic and periodic specifications of embedded systems.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: August 29, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Bharat P. Dave, Niraj K. Jha
  • Patent number: 6112023
    Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: August 29, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Bharat P. Dave, Niraj K. Jha, Ganesh Lakshminarayana
  • Patent number: 6105139
    Abstract: A low-overhead controller-based power management technique that re-specifies control signals to reconfigure existing multiplexer networks and functional units to minimize unnecessary activity. Though the control signals in an RT-level implementation are fully specified, they can be re-specified under certain states/conditions when the data path components that they control need not be active. Another aspect of this invention is an algorithm to perform power management through controller re-specification, that consist of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. The algorithm avoids the above negative effects of controller re-specification.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: August 15, 2000
    Assignee: NEC USA, Inc.
    Inventors: Sujit Dey, Anand Raghunathan, Niraj K. Jha