Abstract: Technologies for through-glass vias with caps are disclosed. In an illustrative embodiment, a substrate core has holes defined in it, and vias are positioned in the holes to carry power or data signals through the substrate core. The vias are formed using bottom-up plating, forming vias that are not anchored to the sidewalls of the holes in the substrate core. The vias can thus move relative to the substrate core, which can mitigate cracking of the core during thermal cycling. In order to mitigate cracking in the build-up layers on the core, the via has a via cap, which can reduce the stress in the build-up layers. Various configurations of such vias are disclosed, and various approaches to fabricate such vias are disclosed.

Abstract: Embodiments disclosed herein include an apparatus that comprises a first layer with a first surface, a second surface, and a sidewall surface that couples the first surface to the second surface. In an embodiment, the first layer comprises a glass layer. In an embodiment, a second layer is on the first surface, the second surface, and the sidewall surface of the first layer. In an embodiment, the second layer is an organic dielectric material. In an embodiment, a third layer is on the second layer, and the third layer is a metallic material. In an embodiment, an edge of the third layer is substantially coplanar with an edge of the second layer.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate that comprises a glass layer. In an embodiment, a frame is provided around the substrate, and a gap is provided between an edge of the substrate and an interior edge of the frame. In an embodiment, a fill layer is provided in the gap, and the fill layer comprises a dielectric material. In an embodiment, a ring is provided over the fill layer around a perimeter of the substrate. In an embodiment, the ring comprises a metallic material.

Abstract: Hybrid panels comprising one or more solid layers of glass positioned within an organic panel are automatically manufactured by a tool link comprising an alignment module, a buffer lamination module, a gap reinforcement module, and a press module. The alignment module places one or more glass layers within an organic frame to form a hybrid panel assembly. The buffer lamination module places a buffer layer on the hybrid panel assembly. The gap reinforcement module places reinforcement material strips over gaps between the frame and the layers of glass and gaps between adjacent layers of glass. Alternatively, the gap reinforcement module dispenses liquid mold material along the gaps. The buffer module performs compression molding on hybrid panel assemblies to form hybrid panels that have planar top and bottom surfaces, and upon which integrated circuit components can be fabricated.

Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarity, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.

Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarly, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.

Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarity, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.

Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Abstract: Applications of smart polymer composites to integrated circuit packaging.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: Applications of smart polymer composites to integrated circuit packaging.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Abstract: A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described.