Patents by Inventor NISHANT LAKHERA
NISHANT LAKHERA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908784Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.Type: GrantFiled: September 23, 2020Date of Patent: February 20, 2024Assignee: NXP USA, Inc.Inventors: Akhilesh Kumar Singh, Andrew Jefferson Mawer, Nishant Lakhera, Chee Seng Foong, Nihaar N. Mahatme
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Publication number: 20230415397Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Patent number: 11787097Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: GrantFiled: February 10, 2021Date of Patent: October 17, 2023Assignee: NXP USA, INC.Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Publication number: 20220250301Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: ApplicationFiled: February 10, 2021Publication date: August 11, 2022Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Publication number: 20220093499Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Akhilesh Kumar Singh, Andrew Jefferson Mawer, Nishant Lakhera, Chee Seng Foong, Nihaar N. Mahatme
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Patent number: 11270972Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.Type: GrantFiled: June 12, 2019Date of Patent: March 8, 2022Assignee: NXP B.V.Inventors: Nishant Lakhera, Akhilesh Kumar Singh, Chee Seng Foong
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Patent number: 11189557Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.Type: GrantFiled: February 14, 2020Date of Patent: November 30, 2021Assignee: NXP USA, INC.Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
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Publication number: 20200395332Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.Type: ApplicationFiled: June 12, 2019Publication date: December 17, 2020Inventors: Nishant LAKHERA, Akhilesh Kumar Singh, Chee Seng Foong
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Publication number: 20200185319Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
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Publication number: 20200013711Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
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Patent number: 10431534Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.Type: GrantFiled: January 8, 2018Date of Patent: October 1, 2019Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
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Publication number: 20190181079Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.Type: ApplicationFiled: January 8, 2018Publication date: June 13, 2019Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
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Publication number: 20190157222Abstract: Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.Type: ApplicationFiled: November 20, 2017Publication date: May 23, 2019Inventors: Nishant LAKHERA, Andrew Jefferson MAWER, Akhilesh Kumar SINGH, Navas Khan ORATTI KALANDAR
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Publication number: 20190103365Abstract: Embodiments for a packaged semiconductor device are provided herein, which includes a substrate; an antenna module attached to a top surface of the substrate, the antenna module including an antenna; an electronic component attached to the top surface of the substrate, the electronic component communicatively coupled to the antenna module through electrical connections in the substrate; a first portion of mold body that encapsulates the antenna module; a second portion of mold body that encapsulates the electronic component, wherein the second portion of mold body is separated from the first portion of mold body by at least a first trench; and a shielding layer that covers the second portion of mold body.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Akhilesh Kumar SINGH, Nishant Lakhera, Navas Khan Oratti Kalandar
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Patent number: 10217698Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: GrantFiled: December 19, 2016Date of Patent: February 26, 2019Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
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Patent number: 10211184Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: GrantFiled: November 3, 2017Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, Navas Khan Oratti Kalandar, Akhilesh K. Singh
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Patent number: 10147645Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.Type: GrantFiled: September 22, 2015Date of Patent: December 4, 2018Assignee: NXP USA, Inc.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
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Patent number: 9978614Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.Type: GrantFiled: June 24, 2016Date of Patent: May 22, 2018Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, James R. Guajardo, Varughese Mathew, Akhilesh K. Singh
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Publication number: 20180114745Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.Type: ApplicationFiled: October 25, 2016Publication date: April 26, 2018Inventors: NAVAS KHAN ORATTI KALANDAR, AKHILESH KUMAR SINGH, NISHANT LAKHERA
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Patent number: 9953904Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.Type: GrantFiled: October 25, 2016Date of Patent: April 24, 2018Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Akhilesh Kumar Singh, Nishant Lakhera