Patents by Inventor NISHANT LAKHERA

NISHANT LAKHERA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9947614
    Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 17, 2018
    Assignee: NXP USA, Inc.
    Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Boon Yew Low, Akhilesh Singh
  • Publication number: 20180053753
    Abstract: A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a substrate, and encapsulating the first surface of the substrate and the plurality of interconnect balls with an encapsulant. A trench is formed in a first surface of the encapsulant exposing a portion the interconnect balls. An interposer is provided having a first interconnect layer. An assembly is formed by attaching connection sites of a first interconnect layer to the exposed portion of the interconnect balls, the first surface of the second substrate extending into the trench.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Navas Khan Oratti Kalandar
  • Publication number: 20180053749
    Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Inventors: Nishant LAKHERA, Navas Khan Oratti KALANDAR, Akhilesh K. SINGH
  • Publication number: 20170278825
    Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Nishant LAKHERA, Navas Khan ORATTI KALANDAR, Akhilesh K. SINGH
  • Publication number: 20170263538
    Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 14, 2017
    Inventors: Navas Khan ORATTI KALANDAR, Nishant LAKHERA, Boon Yew LOW, Akhilesh SINGH
  • Patent number: 9691637
    Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: June 27, 2017
    Assignee: NXP USA, INC.
    Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
  • Publication number: 20170103905
    Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.
    Type: Application
    Filed: October 7, 2015
    Publication date: April 13, 2017
    Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH
  • Publication number: 20170098597
    Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: AKHILESH K. SINGH, RAMA I. HEGDE, NISHANT LAKHERA
  • Publication number: 20170084491
    Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH
  • Patent number: 9559077
    Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
  • Patent number: 9508632
    Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Varughese Mathew, Akhilesh K. Singh
  • Publication number: 20160307780
    Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Nishant LAKHERA, JAMES R. GUAJARDO, VARUGHESE MATHEW, AKHILESH K. SINGH
  • Publication number: 20160118365
    Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 28, 2016
    Inventors: AKHILESH K. SINGH, RAMA I. HEGDE, NISHANT LAKHERA
  • Publication number: 20160064299
    Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: NISHANT LAKHERA, JAMES R. GUAJARDO, VARUGHESE MATHEW, AKHILESH K. SINGH