Patents by Inventor Nishant Rao

Nishant Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176302
    Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 16, 2021
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10896476
    Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 19, 2021
    Assignee: NetSpeed Systems, Inc.
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10749811
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 18, 2020
    Assignee: NetSpeed Systems, Inc.
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Patent number: 10735335
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 4, 2020
    Assignee: NetSpeed Systems, Inc.
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Patent number: 10547514
    Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 28, 2020
    Assignee: NetSpeed Systems, Inc.
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10523599
    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 31, 2019
    Assignee: NetSpeed Systems, Inc.
    Inventors: Eric Norige, Nishant Rao, Sailesh Kumar
  • Patent number: 10469337
    Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 5, 2019
    Inventors: William John Bainbridge, Eric Norige, Sailesh Kumar, Nishant Rao
  • Patent number: 10469338
    Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 5, 2019
    Inventors: William John Bainbridge, Eric Norige, Sailesh Kumar, Nishant Rao
  • Patent number: 10419300
    Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 17, 2019
    Inventors: William John Bainbridge, Eric Norige, Sailesh Kumar, Nishant Rao
  • Publication number: 20190266307
    Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 29, 2019
    Inventors: Nishant RAO, Sailesh KUMAR, Pier Giorgio RAPONI
  • Publication number: 20190260644
    Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.
    Type: Application
    Filed: March 16, 2018
    Publication date: August 22, 2019
    Inventors: Nishant RAO, Sailesh KUMAR, Pier Giorgio RAPONI
  • Publication number: 20190259113
    Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.
    Type: Application
    Filed: August 31, 2018
    Publication date: August 22, 2019
    Inventors: Nishant RAO, Sailesh KUMAR, Pier Giorgio RAPONI
  • Patent number: 10348563
    Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 9, 2019
    Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
  • Patent number: 10298485
    Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 21, 2019
    Inventors: Pier Giorgio Raponi, Sailesh Kumar, Nishant Rao
  • Publication number: 20180324113
    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Inventors: Eric NORIGE, Nishant RAO, Sailesh KUMAR
  • Patent number: 10084725
    Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 25, 2018
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Pier Giorgio Raponi, Nishant Rao, Sailesh Kumar
  • Patent number: 10063496
    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 28, 2018
    Assignee: NETSPEED SYSTEMS INC.
    Inventors: Eric Norige, Nishant Rao, Sailesh Kumar
  • Publication number: 20180227180
    Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Nishant RAO, Sailesh KUMAR, Pier Giorgio RAPONI
  • Publication number: 20180227215
    Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Pier Giorgio RAPONI, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180219738
    Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 2, 2018
    Inventors: William John BAINBRIDGE, Eric NORIGE, Sailesh KUMAR, Nishant RAO