Patents by Inventor Nishant Rao

Nishant Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10084725
    Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 25, 2018
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Pier Giorgio Raponi, Nishant Rao, Sailesh Kumar
  • Patent number: 10063496
    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 28, 2018
    Assignee: NETSPEED SYSTEMS INC.
    Inventors: Eric Norige, Nishant Rao, Sailesh Kumar
  • Publication number: 20180227215
    Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Pier Giorgio RAPONI, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180227180
    Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Nishant RAO, Sailesh KUMAR, Pier Giorgio RAPONI
  • Publication number: 20180219738
    Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 2, 2018
    Inventors: William John BAINBRIDGE, Eric NORIGE, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180198687
    Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Example implementations of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is optimized for a desired implementation during construction of a NoC. The ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a ML predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, and quality metrics obtained by implementing a mapping strategy on the NoC to generate an output that provide an indication as to whether the set of strategies results in a good or bad design or whether the provided strategy meets a threshold for the quality metric.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: Nishant RAO, Pier Giorgio RAPONI, Sailesh KUMAR
  • Publication number: 20180198738
    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 12, 2018
    Inventors: Eric NORIGE, Nishant RAO, Sailesh KUMAR
  • Publication number: 20180197110
    Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Methods, systems, and computer readable mediums of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is actually the most optimal and efficient one or not during construction of a NoC. ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a machine learning algorithm/predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, a quality metrics) obtained by implementing a mapping strategy on the NoC, and one or more performance function (user requirement) to generate an output showing whether the selected strategy for the construction of the NoC yields a good result or a bad result based on learning/training.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: Nishant RAO, Pier Giorgio RAPONI, Sailesh KUMAR
  • Publication number: 20180198734
    Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: Pier Giorgio RAPONI, Nishant RAO, Sailesh KUMAR
  • Publication number: 20180198682
    Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating/constructing NoC based on one or more strategies that are selected by a machine-learning engine (MLE) from a plurality of available strategies based on an input NoC specification. In an aspect, the method can include the steps of processing a Network on Chip (NoC) specification through a process to generate a vector for a plurality of NoC generation strategies, wherein the vector is indicative of which strategies from the plurality of NoC generation strategies are to be used to generate the NoC to meet a quality metric; and generating the NoC by using the strategies from the plurality of NoC generation strategies indicated by the vector as the strategies to be used to generate the NoC, wherein the process is generated through a machine learning process that is trained for the plurality of NoC generation strategies.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 12, 2018
    Inventors: Nishant RAO, Pier Giorgio RAPONI, Sailesh KUMAR
  • Publication number: 20180191626
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 5, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180183722
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180183721
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180159786
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 7, 2018
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Publication number: 20050177567
    Abstract: A method, program and system for searching for files in a computer system employing a Windows operating system is provided. The invention includes receiving search criteria through a Run menu command line, wherein the Run menu is opened by selecting a Start menu, and wherein the search criteria include: a directory and at least one wildcard symbol that represents any number of unspecified characters. The wildcard symbol may represent characters in a file name or character desginating a file type. The search criteria may also include a definite identifying character (e.g., t), which may be part of the file name or file type. The invention searches the directory specified in the search criteria and retrieves a list of the files in the directory that match the search criteria. The invention then opens a window and displays the list of retrieved files.
    Type: Application
    Filed: March 19, 2003
    Publication date: August 11, 2005
    Applicant: International Business Machines Corporation
    Inventors: Nathan Hughes, Nishant Rao, Michelle Uretsky
  • Publication number: 20050089177
    Abstract: An intelligent volume control is provided for an audio system that adjusts a volume level based on several input parameters. The input parameters may vary depending upon the environment of the audio system. The listener may manually set a volume to a desired level relative to environmental noise and interference. The volume level and input parameters are stored as a data point. As values for the input parameters change, the volume control performs statistical analysis on the stored data point to predict a desired volume level. The audio system then adjusts the volume to the predicted level. The listener may then override the volume level and set another data point. Thus, the volume control learns from the volume levels set by the listener and the values of the input parameters.
    Type: Application
    Filed: October 23, 2003
    Publication date: April 28, 2005
    Applicant: International Business Machines Corporation
    Inventors: Nathan Hughes, Nishant Rao, Michelle Uretsky