Patents by Inventor Nitesh Kumar
Nitesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240221084Abstract: A method of facilitating merchant self-service assistance to financing and content support for a marketing event may include receiving a request from a merchant for approval for financing and content generation to support the marketing event and determining whether to approve the merchant based on comparing information provided in the request to approval standards. The method may further include, responsive to approval of the merchant, receiving context information regarding content requested, and providing the content requested to the merchant based on the context information to support the marketing event.Type: ApplicationFiled: March 13, 2024Publication date: July 4, 2024Inventors: Donovan Halpin, Jesse Kendrick, Julia Harrigan, Daniel E. Kaufman, Nitesh Kumar
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Publication number: 20240177233Abstract: A method for exploring lending approval model improvement may include receiving a plurality of loan applications, applying a model to the loan applications to determine an approved set of customers approved for financing under the model and a set of rejected customers rejected for financing under the model, determining, from the set of rejected customers, a selected group of rejected customers and approving the selected group for financing, where loan repayment activity of the selected group defines an exploratory data set, determining, based on the exploratory data set, a set of successful rejected applicants that repay loans associated with the financing for which the selected group was approved, and employing the exploratory data set to evaluate the model for replacement or modification based on the set of successful rejected applicants.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Yonglin Wu, Nitesh Kumar
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Publication number: 20240177133Abstract: A method for providing a voluntary down payment interface in association with a financing offer may include providing, to a remote device of a customer in association with a transaction between a merchant and the customer, an indication of a financing offer associated with a loan, providing, on a same page or screen of the remote device as the indication of the financing offer, a selectable option to display a down payment selector interface for making the voluntary down payment, responsive to the selectable option being selected, displaying the down payment selector interface, and, responsive to the selectable option not being selected, hiding or not displaying the down payment selector interface.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Henry McGowan, Nitesh Kumar, Jesse Kendrick
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Patent number: 11961143Abstract: A method of facilitating merchant self-service assistance to financing and content support for a marketing event may include receiving a request from a merchant for approval for financing and content generation to support the marketing event and determining whether to approve the merchant based on comparing information provided in the request to approval standards. The method may further include, responsive to approval of the merchant, receiving context information regarding content requested, and providing the content requested to the merchant based on the context information to support the marketing event.Type: GrantFiled: June 28, 2022Date of Patent: April 16, 2024Assignee: Affirm, Inc.Inventors: Donovan Halpin, Jesse Kendrick, Julia Harrigan, Daniel E. Kaufman, Nitesh Kumar
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Patent number: 11949971Abstract: A system and a method for automatically identifying key dialogues in media is disclosed herein. In the method disclosed herein, the key dialogues engine receives the media asset and extract transcript data and supplementary data. The key dialogues engine processes the transcript data into a plurality of transcript data elements and associate the transcript data elements with respective data elements selected from the supplementary data.Type: GrantFiled: September 7, 2022Date of Patent: April 2, 2024Assignee: PRIME FOCUS TECHNOLOGIES LIMITEDInventors: Nagaraju Surisetty, Muralidhar Kolar Sridhar, Nitesh Kumar M, Shubham Jaiswal, Suhas Kodandaram Jamadagni, Adrish Bera
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Publication number: 20240089842Abstract: A multi-link device (MLD) operates in a 6 GHz band including a plurality of channels including preferred scanning channels (PSC channels) and non-preferred scanning channels (non-PSC channels), wherein the channels occupy 20 MHz of the 6 GHz band. The MLD includes: a first access point (AP), which initiates its Basic Service Set (BSS) on one of the PSC channels, and sends out Beacon, Probe Response or Fast Initial Link Setup (FILS) discovery frames for association by at least a Station (STA) scanning the 6 GHz band; and at least a second AP, which initiates its BSS on one of the non-PSC channels. The first AP includes information of the second AP in a Neighbour report (NR) or Reduced Neighbour Report (RNR) element in the Beacon, Probe Response or FILS discovery frames.Type: ApplicationFiled: September 7, 2023Publication date: March 14, 2024Applicant: MediaTek Singapore Pte. Ltd.Inventors: Nitesh Kumar Shah, Vinay Garg
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Publication number: 20240053973Abstract: Various systems and methods are described for deployment, import, and scheduling of containers and other software components on cloud and edge computing hardware. A development platform may receive, from a remote location, package data for a deployment of one or more containers, including a configuration for the one or more containers. Such package data may be provided by a Helm chart or a Docker Compose YAML file. The development platform may extract the configuration for the one or more containers from the package data, and also perform a security evaluation of the one or more containers and the configuration for the one or more containers to validate compliance with a security policy. The development platform may execute (and coordinate scheduling) of one or more container images for the one or more containers, based on the configuration, after validating compliance with the security policy.Type: ApplicationFiled: October 24, 2022Publication date: February 15, 2024Inventors: Vidya Ranganathan, Aditya Shukla, Nitesh Kumar, Jitendra Kumar Saini
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Publication number: 20230419409Abstract: A method of facilitating merchant self-service assistance to financing and content support for a marketing event may include receiving a request from a merchant for approval for financing and content generation to support the marketing event and determining whether to approve the merchant based on comparing information provided in the request to approval standards. The method may further include, responsive to approval of the merchant, receiving context information regarding content requested, and providing the content requested to the merchant based on the context information to support the marketing event.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Donovan Halpin, Jesse Kendrick, Julia Harrigan, Daniel E. Kaufman, Nitesh Kumar
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Publication number: 20230420528Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Nitesh Kumar, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Patrick Morrow, Marko Radosavljevic, Jami A. Wiedemer, Subrina Rafique, Mauro J. Kobrinsky
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Publication number: 20230402513Abstract: An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Rohit Galatage, Willy Rachmady, Subrina Rafique, Nitesh Kumar, Cheng-Ying Huang, Jami A. Wiedemer, Nicloe K. Thomas, Munzarin F. Qayyum, Patrick Morrow, Marko Radosavljevic, Mauro J. Kobrinsky
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Publication number: 20230395678Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Munzarin F. Qayyum, Nicole K. Thomas, Jami A. Wiedemer, Jack T. Kavalieros, Marko Radosavljevic, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Nitesh Kumar, Kai Loon Cheong, Venkata Vasiraju
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Publication number: 20230395718Abstract: An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
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Publication number: 20230395717Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
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Publication number: 20230254552Abstract: A system and a method for automatically identifying key dialogues in media is disclosed herein. In the method disclosed herein, the key dialogues engine receives the media asset and extract transcript data and supplementary data. The key dialogues engine processes the transcript data into a plurality of transcript data elements and associate the transcript data elements with respective data elements selected from the supplementary data.Type: ApplicationFiled: September 7, 2022Publication date: August 10, 2023Inventors: Nagaraju Surisetty, Muralidhar Kolar Sridhar, Nitesh Kumar M, Shubham Jaiswal, Suhas Kodandaram Jamadagni, Adrish Bera
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Publication number: 20230207651Abstract: Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Mohammad HASAN, Nitesh KUMAR, Rushabh SHAH, Anand S. MURTHY, Pratik PATEL, Tahir GHANI, Tricia MEYER, Cory BOMBERGER, Glenn A. GLASS, Stephen M. CEA, Anant H. JAHAGIRDAR
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Patent number: 11684738Abstract: Systems and devices for monitoring, detecting, and removing fluid build-up found at various regions along a tracheal tube of an intubated patient. The fluid management system includes pressure and flow sensors for detecting whether there is fluid at the various regions along the tracheal tube, and a means for drawing out the fluid into collection jars. The system also includes lavage features that is able to rinse different the various regions along a tracheal tube. Also disclosed are respiration insertion devices that either couple to existing tracheal tubes or incorporate tracheal tubing, where the respiration insertion body has channels and ports that contact various regions along the tracheal tube. The combination of the fluid management system and the respiration insertion devices effectively monitor and remove fluid at various locations along a tracheal tube of an intubated patient.Type: GrantFiled: June 30, 2020Date of Patent: June 27, 2023Assignee: InnAccell Technologies Private LimitedInventors: Jagdish Chaturvedi, Nitesh Kumar Jangir, Nachiket Deval, Ramakrishna Pappu, Raghuveer Rao, Mohammed Sajid Ali, Vimal Kishore Kakani, Sujay Suresh Kumar Shetty
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Publication number: 20230197818Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Nitesh Kumar, William Hsu, Mohammad Hasan, Ritesh Das, Vivek Thirtha, Biswajeet Guha, Oleg Golonzka
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Publication number: 20230197855Abstract: Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Mohammad HASAN, Nitesh KUMAR, Rushabh SHAH, Anand S. MURTHY, Pratik PATEL, Leonard P. GULER, Tahir GHANI
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Publication number: 20230187509Abstract: Techniques are provided herein to form semiconductor devices having an epi region contact with a high contact area to either or both top and bottom epi regions in a stacked transistor configuration. In one example, two different semiconductor devices include an n-channel device located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A contact structure may be formed that has a greater width when contacting a top surface of the bottom source or drain region than when contacting a side surface of the top source or drain region. The higher contact area on the bottom source or drain region provides a lower contact resistance compared to previous architectures.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Urusa Alaan, Scott B. Clendenning, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Nitesh Kumar
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Patent number: 11638913Abstract: The present disclosure refers to increasing the catalytic efficiency of Weyl semimetals by subjecting Weyl semimetals to an external magnetic field of greater than 0 T, for example greater than 0.1 T. In a preferred embodiment of the present disclosure the Weyl semimetal is selected from the group consisting of NbP, TaP, NbAs and TaAs.Type: GrantFiled: February 6, 2019Date of Patent: May 2, 2023Assignee: MAX PLANCK GESELLSCHAFT ZUR FĂ–RDERUNG DER WISSENSCHAFTEN EVInventors: Chintamani Nagesa Ramachandra Rao, Claudia Felser, Catherine Ranjitha Rajamathi, Nitesh Kumar, Uttam Gupta