Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

Abstract: A system and a method for automatically identifying key dialogues in media is disclosed herein. In the method disclosed herein, the key dialogues engine receives the media asset and extract transcript data and supplementary data. The key dialogues engine processes the transcript data into a plurality of transcript data elements and associate the transcript data elements with respective data elements selected from the supplementary data.

Abstract: Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

Abstract: Systems and devices for monitoring, detecting, and removing fluid build-up found at various regions along a tracheal tube of an intubated patient. The fluid management system includes pressure and flow sensors for detecting whether there is fluid at the various regions along the tracheal tube, and a means for drawing out the fluid into collection jars. The system also includes lavage features that is able to rinse different the various regions along a tracheal tube. Also disclosed are respiration insertion devices that either couple to existing tracheal tubes or incorporate tracheal tubing, where the respiration insertion body has channels and ports that contact various regions along the tracheal tube. The combination of the fluid management system and the respiration insertion devices effectively monitor and remove fluid at various locations along a tracheal tube of an intubated patient.

Abstract: Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

Abstract: Techniques are provided herein to form semiconductor devices having an epi region contact with a high contact area to either or both top and bottom epi regions in a stacked transistor configuration. In one example, two different semiconductor devices include an n-channel device located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A contact structure may be formed that has a greater width when contacting a top surface of the bottom source or drain region than when contacting a side surface of the top source or drain region. The higher contact area on the bottom source or drain region provides a lower contact resistance compared to previous architectures.

Abstract: The present disclosure refers to increasing the catalytic efficiency of Weyl semimetals by subjecting Weyl semimetals to an external magnetic field of greater than 0 T, for example greater than 0.1 T. In a preferred embodiment of the present disclosure the Weyl semimetal is selected from the group consisting of NbP, TaP, NbAs and TaAs.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for improving remote direct memory access (RDMA) performance. A method for improving RDMA performance occurs at an RDMA node utilizing a user space and a kernel space for executing software. The method includes posting, by an application executing in the user space, an RDMA work request including a data element indicating a plurality of RDMA requests associated with the RDMA work request to be generated by software executing in the kernel space; and generating and sending, by the software executing in the kernel space, the plurality of RDMA requests to or via a system under test (SUT).

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

Abstract: An information handling system includes first and second memories, and a processor. The first memory stores user settings for performing a search in a system management console. The second memory stores data associated with components of the system management console. The processor receives multiple user defined weights, and each of the user defined weights is associated with a different search criterion of multiple search criteria. Based on the received user defined weights, the processor determines updated weights for each of the search criteria. The processor stores the updated weights for each of the search criteria in the user setting of the first memory. The processor receives a search query, and provides search results based on the search query and the updated weights for each of the search criteria. The search results include data from the second memory.

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.

Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires. The epitaxial growth occurs inside a mold confinement, and due the mold, the lateral wingspan of the wingspan of the epitaxial growth is limited. Also the mold causes the epitaxial source or drain structures to exhibit substantially vertical opposing sidewalls and a top surface having a generally mushroom shape over a top of a dielectric layer.

Abstract: Gate-all-around integrated circuit structures having reduced gate height structures and subfins, and method of fabricating gate-all-around integrated circuit structures having reduced gate height structures, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a subfin, and an isolation structure on either side of the subfin. A gate stack is over the plurality of nanowires, around individual nanowires, and over the subfin. Gate spacers are on either side of the gate stack, and a dielectric capping material is inside the gate spacers with shoulder portions inside the gate stack.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making semiconductor devices. In an embodiment, a semiconductor device comprises a substrate, where the substrate is a dielectric material, and a vertical stack of semiconductor channels over the substrate. In an embodiment, the semiconductor device further comprises a source at a first end of the semiconductor channels, a drain at a second end of the semiconductor channels, and a barrier between a bottom surface of the source and the substrate.

Abstract: A method and system for assigning and tracking progress of action items in a review meeting comprises extracting action items from a meeting document during the review meeting once the review meeting is initiated between the reviewee and the reviewer. The method comprises identifying reviewee content and reviewer content by using feature extraction technique on audio snippets spoken by the reviewee and the reviewer during the review meeting. The method further comprises determining whether the review meeting is a first meeting or a subsequent meeting, between the reviewee and the reviewer, for discussing the action items extracted from the meeting document. Based on the determination, action items for reviewee and reviewer are assigned and the status of the previously assigned action items of reviewee and previously assigned action items of reviewer are tracked.

Abstract: The present invention provides an integrated wireless access backhaul device for network densification using a mesh network includes at least one integrated access and backhaul module with a first backhaul interface using one optical wireless communication links, a second backhaul interface using V-band links, an access interface providing a radio link to a user equipment and a switch fabric to transfer data between the first backhaul interface, the second backhaul interface and the access interface in real-time.

Abstract: The present invention relates to a method for providing a contiguous slot in an unlicensed band of radio slots by a cloud intelligence engine including steps of selecting a plurality of non-contiguous slots in the unlicensed band of radio slots, determining an interference score for each of the plurality of non-contiguous slots, creating the contiguous slot by combining at least two non-contiguous slots based on the determined interference score and allocating at least combined two non-contiguous slots from the plurality of non-contiguous slots as the contiguous slot.

Abstract: An active audio-visual system and method for identifying events occurring at a location-of-interest is provided. In particular, a system that comprises a Fisheye image capturing device, an audio module and a computing module communicatively coupled to both the image capturing device and the audio module whereby all the modules and devices are provided at the location-of-interest is provided. In operation, the audio module is configured to issue a notification to the computing module when an audio event is detected at the location-of-interest. The notification, which will contain a point of origin of the audio event, will then be used by the computing module to cause the calibrated Fisheye image capturing device to provide a captured high-resolution perspective image of the point of origin of the audio signal to an event identification module for further processing.

Abstract: A vehicle system for a vehicle includes a controller configured to: identify a user profile to be loaded based on communication with a user device; receive user preference packets containing a user ID from the user device; determine whether the user ID of the user preference packets matches with a user ID of the user profile to be loaded; and discard the user preference packets in response to determining that the user ID of the user preference packets does not match with the user ID of the user profile to be loaded.