Patents by Inventor Niti Goel
Niti Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685381Abstract: Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.Type: GrantFiled: June 28, 2013Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Niti Goel, Ravi Pillarisetty, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey, Benjamin Chu-Kung, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
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Publication number: 20170162453Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Han Wui Then, Niloy Mukherjee, Matthew V. Metz, Robert S. Chau
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Publication number: 20170154981Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.Type: ApplicationFiled: February 10, 2017Publication date: June 1, 2017Inventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
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Patent number: 9666583Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.Type: GrantFiled: June 8, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
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Publication number: 20170148728Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: June 27, 2014Publication date: May 25, 2017Inventors: Silvio E. BOU-GHAZALE, Rany T. ELSAYED, Niti GOEL
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Patent number: 9653559Abstract: A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.Type: GrantFiled: December 27, 2011Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Niloy Mukherjee, Gilbert Dewey, Marko Radosavljevic, Niti Goel, Sanaz Kabehie, Matthew V. Metz, Robert S. Chau
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Publication number: 20170133497Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel, Sanaz Kabehie Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
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Publication number: 20170125524Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Applicants: Intel Corporation, Intel CorporationInventors: RAVI PILLARISETTY, SANSAPTAK DASGUPTA, NITI GOEL, VAN H. LE, MARKO RADOSAVLJEVIC, GILBERT DEWEY, NILOY MUKHERJEE, MATTHEW V. METZ, WILLY RACHMADY, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, HAROLD W. KENNEL, STEPHEN M. CEA, ROBERT S. CHAU
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Patent number: 9640622Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.Type: GrantFiled: June 28, 2013Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
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Patent number: 9640537Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: GrantFiled: September 27, 2013Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
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Patent number: 9634007Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: GrantFiled: June 11, 2014Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Han Wui Then, Niloy Mukherjee, Matthew V. Metz, Robert S. Chau
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Publication number: 20170077050Abstract: Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.Type: ApplicationFiled: June 25, 2014Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RANY T. ELSAYED, NITI GOEL, SILVIO E. BOU-GHAZALE, ANSHUMALI ROY, JOSEPH C. YIP
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Patent number: 9590069Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.Type: GrantFiled: June 26, 2015Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel, Sanaz Kabehie Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
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Patent number: 9583396Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.Type: GrantFiled: June 28, 2013Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
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Patent number: 9570614Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.Type: GrantFiled: September 27, 2013Date of Patent: February 14, 2017Assignee: Intel CorporationInventors: Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Willy Rachmady, Jack T. Kavalieros, Benjamin Chu-Kung, Harold W. Kennel, Stephen M. Cea, Robert S. Chau
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TECHNIQUES TO ACHIEVE AREA REDUCTION THROUGH CO-OPTIMIZING LOGIC CORE BLOCKS AND MEMORY REDUNDANCIES
Publication number: 20170023863Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.Type: ApplicationFiled: July 8, 2014Publication date: January 26, 2017Applicant: INTEL CORPORATIONInventors: SILVIO E. BOU-GHAZALE, ABHIK GHOSH, NITI GOEL -
Publication number: 20170018543Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.Type: ApplicationFiled: June 25, 2014Publication date: January 19, 2017Applicant: INTEL CORPORATIONInventors: Rany T. ELSAYED, Niti GOEL, Silvio E. BOU-GHAZALE, Randy J. AKSAMIT
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Publication number: 20160211263Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: ApplicationFiled: September 27, 2013Publication date: July 21, 2016Inventors: Niti GOEL, Robert S. CHAU, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Matthew V. METZ, Niloy MUKHERJEE, Nancy M. ZELICK, Gilbert DEWEY, Willy RACHMADY, Marko RADOSAVLJEVIC, Van H. LE, Ravi PILLARISETTY, Sansaptak DASGUPTA
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Publication number: 20160204037Abstract: Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.Type: ApplicationFiled: June 28, 2013Publication date: July 14, 2016Applicant: INTEL CORPORATIONInventors: Niti Goel, Ravi Pillarisetty, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey, Benjamin Chu-Kung, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
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Publication number: 20160204246Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Applicants: Intel Corporation, Intel CorporationInventors: RAVI PILLARISETTY, SANSAPTAK DASGUPTA, NITI GOEL, VAN H. LE, MARKO RADOSAVLJEVIC, GILBERT DEWEY, NILOY MUKHERJEE, MATTHEW V. METZ, WILLY RACHMADY, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, HAROLD W. KENNEL, STEPHEN M. CEA, ROBERT S. CHAU