Patents by Inventor Niti Goel
Niti Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160204263Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Inventors: Niloy MUKHERJEE, Marko RADOSAVLJEVIC, Jack T. KAVALIEROS, Ravi PILLARISETTY, Niti GOEL, Van H. LE, Gilbert DEWEY, Benjamin CHU-KUNG
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Publication number: 20160204036Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.Type: ApplicationFiled: June 28, 2013Publication date: July 14, 2016Applicant: INTEL CORPORATIONInventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
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Publication number: 20160204208Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.Type: ApplicationFiled: June 28, 2013Publication date: July 14, 2016Inventors: Niti GOEL, Gilbert DEWEY, Niloy MUKHERJEE, Matthew V. METZ, Marko RADOSAVLJEVIC, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
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Patent number: 9391181Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.Type: GrantFiled: December 21, 2012Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack T. Kavalieros, Matthew V. Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy M. Zelick
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Publication number: 20160181099Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (I) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.Type: ApplicationFiled: September 4, 2013Publication date: June 23, 2016Inventors: Niloy MUKHERJEE, Niti GOEL, Sanaz K. GARDNER, Pragyansri PATHI, Matthew V. METZ, Sansaptak DASGUPTA, Seung Hoon SUNG, James M. POWERS, Gilbert DEWEY, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
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Publication number: 20150318375Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.Type: ApplicationFiled: June 26, 2015Publication date: November 5, 2015Inventors: Sansaptak Dasgupta, Han Wui THEN, Marko RADOSAVLJEVIC, Niloy MUKHERJEE, Niti GOEL, Sanaz Kabehie GARDNER, Seung Hoon SUNG, Ravi PILLARISETTY, Robert S. CHAU
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Publication number: 20150270265Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.Type: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
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Patent number: 9112028Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.Type: GrantFiled: April 28, 2014Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
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Patent number: 9099490Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.Type: GrantFiled: September 28, 2012Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel, Sanaz Kabehie, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
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Patent number: 9054190Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.Type: GrantFiled: April 28, 2014Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
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Publication number: 20150123171Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.Type: ApplicationFiled: January 14, 2015Publication date: May 7, 2015Inventors: MARKO RADOSAVLJEVIC, PRASHANT MAJHI, JACK T. KAVALIEROS, NITI GOEL, WILMAN TSAI, NILOY MUKHERJEE, YONG JU LEE, GILBERT DEWEY, WILLY RACHMADY
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Patent number: 8936976Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.Type: GrantFiled: December 23, 2009Date of Patent: January 20, 2015Assignee: Intel CorporationInventors: Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai, Niloy Mukherjee, Yong Ju Lee, Gilbert Dewey, Willy Rachmady
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Patent number: 8872225Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.Type: GrantFiled: December 20, 2012Date of Patent: October 28, 2014Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Van Le, Robert Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy Zelick
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Publication number: 20140291726Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Ravi Pillarisetty, Seung Hoon SUNG, Niti GOEL, Jack T. KAVALIEROS, Sansaptak DASGUPTA, Van H. LE, Willy RACHMADY, Marko RADOSAVLJEVIC, Gilbert DEWEY, Han Wui THEN, Niloy MUKHERJEE, Matthew V. METZ, Robert S. Chau
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Publication number: 20140231871Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: INTEL CORPORATIONInventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
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Publication number: 20140203326Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.Type: ApplicationFiled: December 28, 2011Publication date: July 24, 2014Inventors: Niloy Mukherjee, Matthew V. Metz, james m. Powers, Van H. Le, Benjamin Chu-Kung, Mark R. Lemay, Marko Radosavljevic, Niti Goel
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Patent number: 8785907Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.Type: GrantFiled: December 20, 2012Date of Patent: July 22, 2014Assignee: Intel CorporationInventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van H. Le, Matthew V. Metz, Jack T. Kavalieros, Ravi Pillarisetty, Sanaz K. Gardner, Sansaptak Dasgupta, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic, Gilbert Dewey, Marc C. French, Jessica Kachian, Satyarth Suri, Robert S. Chau
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Patent number: 8765563Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.Type: GrantFiled: September 28, 2012Date of Patent: July 1, 2014Assignee: Intel CorporationInventors: Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Han Wui Then, Niloy Mukherjee, Matthew V. Metz, Robert S. Chau
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Publication number: 20140175378Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van Le, Matthew Metz, Jack Kavalieros, RAVI PILLARISETTY, Sanaz Gardner, SANSAPTAK DASGUPTA, Willy Rachmady, BENJAMIN CHU-KUNG, MARKO RADOSAVLJEVIC, Gilbert Dewey, Marc French, JESSICA KACHIAN, SATYARTH SURI, Robert Chau
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Publication number: 20140175512Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: BENJAMIN CHU-KUNG, VAN LE, ROBERT CHAU, SANSAPTAK DASGUPTA, GILBERT DEWEY, NITI GOEL, JACK KAVALIEROS, MATTHEW METZ, NILOY MUKHERJEE, RAVI PILLARISETTY, WILLY RACHMADY, MARKO RADOSAVLJEVIC, HAN WUI THEN, NANCY ZELICK