Patents by Inventor Nitin Agarwal

Nitin Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7598816
    Abstract: A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Nitin Agarwal, Kallol Chatterjee
  • Patent number: 7595744
    Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: September 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Ramesh Kumar Singh, Visvesvaraya A Pentakota, Dantes John, Supreet Joshi
  • Patent number: 7576668
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: August 18, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Vikas Kumar Sinha, Nitin Agarwal, Visvesvararaya A. Pentakota, Sandeep Oswal
  • Patent number: 7573414
    Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Abhaya Kumar, Visvesvarya Pentakota, Nitin Agarwal, Jagannathan Venkataraman
  • Publication number: 20090184853
    Abstract: An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 23, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Hariraj Udupa, Neeraj Shrivastava, Nitin Agarwal
  • Publication number: 20090146857
    Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 11, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhaya Kumar, Visvesvarya Pentakota A, Nitin Agarwal, Jagannathan Venkataraman
  • Publication number: 20090135037
    Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Ramesh Kumar Singh, Visvesvaraya A. Pentakota, Dantes John, Supreet Joshi
  • Publication number: 20090091487
    Abstract: Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved.
    Type: Application
    Filed: October 4, 2007
    Publication date: April 9, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagarajan Viswanathan, Nitin Agarwal, Jagannathan Venkataraman, Visvesvaraya Pentakota, Abhaya Kumar
  • Patent number: 7479915
    Abstract: A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 20, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Ramesh Kumar Singh, Nitin Agarwal, Abhaya Kumar, Visvesvarya Pentakota A
  • Publication number: 20080218151
    Abstract: A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage.
    Type: Application
    Filed: December 26, 2007
    Publication date: September 11, 2008
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventor: Nitin Agarwal
  • Publication number: 20080055129
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Application
    Filed: November 2, 2007
    Publication date: March 6, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Udupa, Vikas Sinha, Nitin Agarwal, Visvesvararaya Pentakota, Sandeep Oswal
  • Publication number: 20080048899
    Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.
    Type: Application
    Filed: August 25, 2006
    Publication date: February 28, 2008
    Inventor: Nitin Agarwal
  • Patent number: 7327300
    Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 5, 2008
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventor: Nitin Agarwal
  • Publication number: 20080018369
    Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.
    Type: Application
    Filed: January 3, 2007
    Publication date: January 24, 2008
    Inventors: Kallol Chatterjee, Nitin Agarwal
  • Patent number: 7310058
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: December 18, 2007
    Assignee: Texas Instruments (India) Private Limited Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Vikas Kumar Sinha, Nitin Agarwal, Visvesvaraya A. Pentakota, Sandeep Oswal
  • Patent number: 7286003
    Abstract: An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 23, 2007
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Kallol Chatterjee, Nitin Agarwal
  • Publication number: 20070229175
    Abstract: The invention relates to an improved phase locked loop (PLL) circuit for preventing erroneous condition in the charge pump operation. The invention includes modification in the PLL circuitry by adding delay elements for connection between the phase frequency detector and the charge pump and a digital logic circuit for obtaining the clock signals for the loop filter.
    Type: Application
    Filed: December 12, 2006
    Publication date: October 4, 2007
    Applicant: STMicroelectronics PVT. LTD.
    Inventors: Nitin Agarwal, Kallol Chatterjee
  • Publication number: 20070182456
    Abstract: An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form (single-ended or differential) of outputs are being provided, outputs in the other form are disabled. Outputs in differential form may be provided at twice the frequency as compared to the outputs in single-ended form. As a result the same number of pins can be supported for both single-ended and differential outputs for a desired data throughput, and the pin count of the integrated circuit is reduced.
    Type: Application
    Filed: November 20, 2006
    Publication date: August 9, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Eduardo Bartolome, Sandeep Oswal, Visvesvaraya Pentakota, Jagannathan Venkataraman, Nagarajan Viswanathan, Vinod Paliakara
  • Publication number: 20070013569
    Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
    Type: Application
    Filed: July 13, 2005
    Publication date: January 18, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Udupa, Vikas Sinha, Nitin Agarwal, Visvesvaraya PENTAKOTA, Sandeep Oswal
  • Patent number: 7161521
    Abstract: According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam Salil Nandi, Visvesvaraya A. Pentakota, Nitin Agarwal, Sandeep Kesrimal Oswal